The TMS320C6000 Optimization Workshop focuses on writing high performance code for the TMS320C6000 DSP.  By examining the CPU architecture, TI DSP Development Tools, and other system issues you should leave the class with a good understanding of the techniques involved in writing good C6000 code. While high performance coding is the primary concern, the workshop also addresses other important system optimization topics: minimizing code size; numerical issues with fixed-point processors; writing interruptible, high-speed code; cache memory and packaging xDAIS algorithms.

By thoroughly investigating fundamental aspects of the TMS320C6000 VelociTI^TM  architecture, combined with coding techniques such as software pipelining, you will have a solid understanding of how this multiple issue processor obtains its high performance. In addition you will have the knowledge necessary to make tradeoffs between processor performance and system memory requirements.  

This workshop covers the architecture of all C6000 devices including C62x, C67x/C672x, C64x/C64x+.

 Course Content

The course begins with an exploration of the C6000’s CPU architecture. By the first afternoon you will begin creating Code Composer Studio projects and running C programs.

After covering the basic elements of writing C6000 code, you will learn performance and size optimization techniques for C6000 code. The workshop concludes with a series of system-related topics – from fixed-point numerical issues to an examination of internal memory and cache.

  Workshop Outline 

Day 1

 1.  Architectural Overview

 2.  Using CCS with C Programs

 3.  Introduction to the Hardware Pipeline  

Day 2

 4.  Calling Assembly from C

 5.  Using the Assembly Optimizer

 6.  Architectural Details

 7.  Optimization Methods

 8.  Software Pipelining

Day 3

 9.   Advanced C Performance Optimizations

10.  Optimizing C Code for Size

11.  Basic Memory Management

12.  Advanced Memory Management

13.  Packaging an Algorithm   

Day 4

14.  Using Cache memory

15.  Optimizing Interruptible Code

16.  Numerical Issues

 Course Prerequisites

This workshop is primarily intended for software engineers writing code and algorithms for the C6000 family. It will also be useful for system designers evaluating the C6000´s CPU architecture.

The course has no specific prerequisites. However, some familiarity with the following is helpful:

• C programming language
• System design with embedded processors
• Compiling, assembling, and linking code; reading processor memory-maps
• Digital signal processing

While DSP theory is not specifically covered in the workshop, understanding DSP concepts may help you better understand their implementation with a digital signal processor.

Whether you plan to write your C6000 application using the C language or Linear Assembly language, you will find this workshop addresses your code writing and optimization needs. If you are evaluating the C6000 CPU architecture or want to learn how to write better C and assembly code for the C6000, this Optimization workshop is a good choice.

However, if you are tasked with building a system around the C6000 and your job includes: system design, using the C6000 peripherals to move data on/off-chip, scheduling real-time software and designing your system's boot-up procedure–you may find that this workshop does not suit your needs.

  Workshop Pricing and Schedule

 European and USA Multi-day workshops are conducted in English

 Course Details

• Classes begin at 8:30 a.m. and run through 5:30 p.m. each day. You can expect to finish class between 2:00pm - 4:00pm on the final day
• Click on "Locations" on the left navigation bar for directions to the training facility and information on payment options

 Cancellation Policy 

• European classes are subject to cancellation if minimum number of attendees is not  met one week prior to the date of the workshop.  
• US classes are subject to cancellation if minimum number of attendees is not met two weeks prior to  the date of the workshop.
• In the event of short notice cancellation Texas Instruments' liability is limited solely to the refund of workshop fees.

   Minimum = 5   Maximum = 12