SPRSP81B
October 2023 – March 2024
AM263P4
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
3.1
Functional Block Diagram
4
Device Comparison
4.1
Related Products
5
Terminal Configuration and Functions
5.1
Pin Diagram
5.1.1
ZCZ_C Pin Diagram
5.1.2
ZCZ_S Pin Diagram
5.1.3
ZCZ_F Pin Diagram
5.2
Pin Attributes
14
15
5.3
Signal Descriptions
17
5.3.1
ADC
19
20
21
22
23
5.3.1.1
ADC-CMPSS Signal Connections
5.3.2
ADC Resolver
26
27
28
5.3.3
ADC_CAL
30
5.3.4
ADC VREF
32
5.3.5
CPSW
34
35
36
37
38
39
40
5.3.6
CPTS
42
5.3.7
DAC
44
5.3.8
EPWM
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
5.3.9
EQEP
79
80
81
5.3.10
FSI
83
84
85
86
87
88
89
90
5.3.11
GPIO
92
5.3.12
I2C
94
95
96
97
98
5.3.13
LIN
100
101
102
103
104
5.3.14
MCAN
106
107
108
109
110
111
112
113
5.3.15
SPI (MCSPI)
115
116
117
118
119
120
121
122
5.3.16
MMC
124
5.3.17
OSPI (Shared)
126
5.3.18
Power Supply
128
5.3.19
PRU-ICSS
130
131
132
133
134
5.3.20
SDFM
136
137
5.3.21
System and Miscellaneous
5.3.21.1
Boot Mode Configuration
140
5.3.21.2
Clocking
142
143
144
5.3.21.3
Emulation and Debug
146
147
5.3.21.4
SYSTEM
149
5.3.21.5
VMON
151
5.3.21.6
Reserved
153
5.3.22
UART
155
156
157
158
159
160
5.3.23
XBAR
162
163
Pin Connectivity Requirements
6
Specifications
6.1
Absolute Maximum Ratings
6.2
Electrostatic Discharge (ESD) Extended Automotive Ratings
6.3
Electrostatic Discharge (ESD) Industrial Ratings
6.4
Power-On Hours (POH) Summary
6.4.1
Automotive Temperature Profile
6.5
Recommended Operating Conditions
6.6
Operating Performance Points
6.7
Power Consumption Summary
6.7.1
Power Consumption - Maximum
6.8
Electrical Characteristics
6.8.1
Digital and Analog IO Electrical Characteristics
6.8.2
Analog to Digital Converter Characteristics
6.8.2.1
Analog-to-Digital Converter (ADC)
6.8.2.2
Resolver Analog-to-Digital Converter (ADC_R)
6.8.2.3
ADC Input Model
6.8.3
Comparator Subsystem A (CMPSSA)
6.8.4
Comparator Subsystem B (CMPSSB)
6.8.5
Digital-to-Analog Converter (DAC)
6.8.6
Power Management Unit (PMU)
6.8.7
Safety Comparators
6.9
VPP Specifications for One-Time Programmable (OTP) eFuses
6.9.1
VPP Specifications
6.9.2
Hardware Requirements
6.9.3
Programming Sequence
6.9.4
Impact to Your Hardware Warranty
6.10
Thermal Resistance Characteristics
6.10.1
Package Thermal Characteristics
6.11
Timing and Switching Characteristics
6.11.1
Timing Parameters and Information
6.11.2
Power Supply Sequencing
6.11.2.1
Power-On and Reset Sequencing
6.11.2.1.1
Power Reset Sequence Description
6.11.2.2
Power-Down Sequencing
6.11.3
System Timing
6.11.3.1
System Timing Conditions
6.11.3.2
Reset Timing
6.11.3.2.1
PORz Timing Requirements
203
6.11.3.2.2
WARMRSTn Switching Characteristics
205
6.11.3.2.3
WARMRSTn Timing Requirements
207
6.11.3.3
Safety Signal Timing
6.11.3.3.1
SAFETY_ERRORn Switching Characteristics
210
6.11.4
Clock Specifications
6.11.4.1
Input Clocks / Oscillators
6.11.4.1.1
Crystal Oscillator (XTAL) Parameters
6.11.4.1.2
External Clock Characteristics
6.11.5
Peripherals
6.11.5.1
2-port Gigabit Ethernet MAC (CPSW)
6.11.5.1.1
CPSW MDIO Timing
6.11.5.1.1.1
CPSW MDIO Timing Conditions
6.11.5.1.1.2
CPSW MDIO Timing Requirements
6.11.5.1.1.3
CPSW MDIO Switching Characteristics
221
6.11.5.1.2
CPSW RGMII Timing
6.11.5.1.2.1
CPSW RGMII Timing Conditions
6.11.5.1.2.2
CPSW RGMII[x]_RCLK Timing Requirements - RGMII Mode
6.11.5.1.2.3
CPSW RGMII[x]_RD[3:0], and RGMII[x]_RCTL Timing Requirements
226
6.11.5.1.2.4
CPSW RGMII[x]_TCLK Switching Characteristics - RGMII Mode
6.11.5.1.2.5
CPSW RGMII[x]_TD[3:0], and RGMII[x]_TCTL Switching Characteristics - RGMII Mode
229
6.11.5.1.3
CPSW RMII Timing
6.11.5.1.3.1
CPSW RMII Timing Conditions
6.11.5.1.3.2
CPSW RMII[x]_REFCLK Timing Requirements - RMII Mode
233
6.11.5.1.3.3
CPSW RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER Timing Requirements - RMII Mode
235
6.11.5.1.3.4
CPSW RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics - RMII Mode
237
6.11.5.2
Enhanced Capture (eCAP)
6.11.5.2.1
ECAP Timing Conditions
6.11.5.2.2
ECAP Timing Requirements
241
6.11.5.2.3
ECAP Switching Characteristics
243
6.11.5.3
Enhanced Pulse Width Modulation (ePWM)
6.11.5.3.1
EPWM Timing Conditions
6.11.5.3.2
EPWM Timing Requirements
247
6.11.5.3.3
EPWM Switching Characteristics
249
EPWM Characteristics
6.11.5.4
Enhanced Quadrature Encoder Pulse (eQEP)
6.11.5.4.1
EQEP Timing Conditions
6.11.5.4.2
EQEP Timing Requirements
254
6.11.5.4.3
EQEP Switching Characteristics
6.11.5.5
Fast Serial Interface (FSI)
6.11.5.5.1
FSI Timing Conditions
6.11.5.5.2
FSIRX Timing Requirements
259
6.11.5.5.3
FSIRX Switching Characteristics
6.11.5.5.4
FSITX Switching Characteristics
262
6.11.5.5.5
FSITX SPI Signaling Mode Switching Characteristics
264
6.11.5.6
General Purpose Input/Output (GPIO)
6.11.5.6.1
GPIO Timing Conditions
6.11.5.6.2
GPIO Timing Requirements
6.11.5.6.3
GPIO Switching Characteristics
6.11.5.7
Inter-Integrated Circuit (I2C)
6.11.5.7.1
I2C
6.11.5.8
Local Interconnect Network (LIN)
6.11.5.8.1
LIN Timing Conditions
6.11.5.8.2
LIN Timing Requirements
6.11.5.8.3
LIN Switching Characteristics
6.11.5.9
Modular Controller Area Network (MCAN)
6.11.5.9.1
MCAN Timing Conditions
6.11.5.9.2
MCAN Switching Characteristics
6.11.5.10
Serial Peripheral Interface (SPI)
6.11.5.10.1
SPI Timing Conditions
6.11.5.10.2
SPI Controller Mode Timing Requirements
281
6.11.5.10.3
SPI Controller Mode Switching Characteristics (Clock Phase = 0)
283
6.11.5.10.4
SPI Peripheral Mode Timing Requirements
285
6.11.5.10.5
SPI Peripheral Mode Switching Characteristics
287
6.11.5.11
Multi-Media Card/Secure Digital (MMCSD)
6.11.5.11.1
MMC Timing Conditions
6.11.5.11.2
MMC Timing Requirements - SD Card Default Speed Mode
291
6.11.5.11.3
MMC Switching Characteristics - SD Card Default Speed Mode
293
6.11.5.11.4
MMC Timing Requirements - SD Card High Speed Mode
295
6.11.5.11.5
MMC Switching Characteristics - SD Card High Speed Mode
297
6.11.5.12
Octal Serial Peripheral Interface (OSPI)
6.11.5.12.1
OSPI Timing Conditions
6.11.5.12.2
OSPI PHY Mode
6.11.5.12.2.1
OSPI0 With PHY Data Training
6.11.5.12.2.1.1
OSPI DLL Delay Mapping for PHY Data Training
6.11.5.12.2.1.2
OSPI Timing Requirements - PHY Data Training
304
6.11.5.12.2.1.3
OSPI Switching Characteristics - PHY Data Training
306
6.11.5.12.2.2
OSPI0 Without Data Training
6.11.5.12.2.2.1
OSPI0 PHY SDR Timing
6.11.5.12.2.2.1.1
OSPI DLL Delay Mapping for PHY SDR Timing Modes
6.11.5.12.2.2.1.2
OSPI Timing Requirements - PHY SDR Mode
311
6.11.5.12.2.2.1.3
OSPI Switching Characteristics - PHY SDR Mode
313
6.11.5.12.2.2.2
OSPI0 PHY DDR Timing
6.11.5.12.2.2.2.1
OSPI DLL Delay Mapping for PHY DDR Timing Modes
6.11.5.12.2.2.2.2
OSPI Timing Requirements - PHY DDR Mode
317
6.11.5.12.2.2.2.3
OSPI Switching Characteristics - PHY DDR Mode
319
6.11.5.12.3
OSPI Tap Mode
6.11.5.12.3.1
OSPI0 Tap SDR Timing
6.11.5.12.3.1.1
OSPI Timing Requirements - Tap SDR Mode
323
6.11.5.12.3.1.2
OSPI Switching Characteristics - Tap SDR Mode
325
6.11.5.12.3.2
OSPI0 Tap DDR Timing
6.11.5.12.3.2.1
OSPI Timing Requirements - Tap DDR Mode
328
6.11.5.12.3.2.2
OSPI Switching Characteristics - Tap DDR Mode
330
6.11.5.13
Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
6.11.5.13.1
PRU-ICSS Programmable Real-Time Unit (PRU)
6.11.5.13.1.1
PRU-ICSS PRU Timing Conditions
6.11.5.13.1.2
PRU-ICSS PRU Switching Characteristics - Direct Output Mode
335
6.11.5.13.1.3
PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
337
6.11.5.13.1.4
PRU-ICSS PRU Timing Requirements - Shift In Mode
339
6.11.5.13.1.5
PRU-ICSS PRU Switching Characteristics - Shift Out Mode
341
6.11.5.13.2
PRU-ICSS PRU Sigma Delta and Peripheral Interface
6.11.5.13.2.1
PRU-ICSS PRU Sigma Delta and Peripheral Interface Timing Conditions
6.11.5.13.2.2
PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
345
6.11.5.13.2.3
PRU-ICSS PRU Timing Requirements - Peripheral Interface Mode
347
6.11.5.13.2.4
PRU-ICSS PRU Switching Characteristics - Peripheral Interface Mode
349
6.11.5.13.3
PRU-ICSS Pulse Width Modulation (PWM)
6.11.5.13.3.1
PRU-ICSS PWM Timing Conditions
6.11.5.13.3.2
PRU-ICSS PWM Switching Characteristics
353
6.11.5.13.4
PRU-ICSS Industrial Ethernet Peripheral (IEP)
6.11.5.13.4.1
PRU-ICSS IEP Timing Conditions
6.11.5.13.4.2
PRU-ICSS IEP Timing Requirements - Input Validated with SYNCx
357
6.11.5.13.4.3
PRU-ICSS IEP Timing Requirements - Digital IOs
359
6.11.5.13.4.4
PRU-ICSS IEP Timing Requirements - LATCHx_IN
361
6.11.5.13.5
PRU-ICSS Universal Asynchronous Receiver Transmitter (UART)
6.11.5.13.5.1
PRU-ICSS UART Timing Conditions
6.11.5.13.5.2
PRU-ICSS UART Timing Requirements
6.11.5.13.5.3
PRU-ICSS UART Switching Characteristics
366
6.11.5.13.6
PRU-ICSS Enhanced Capture Peripheral (ECAP)
6.11.5.13.6.1
PRU-ICSS ECAP Timing Conditions
6.11.5.13.6.2
PRU-ICSS ECAP Timing Requirements
370
6.11.5.13.6.3
PRU-ICSS ECAP Switching Characteristics
372
6.11.5.13.7
PRU-ICSS MDIO and MII
6.11.5.13.7.1
PRU-ICSS MDIO Timing
6.11.5.13.7.1.1
PRU-ICSS MDIO Timing Conditions
6.11.5.13.7.1.2
PRU-ICSS MDIO Timing Requirements
6.11.5.13.7.1.3
PRU-ICSS MDIO Switching Characteristics
378
6.11.5.13.7.2
PRU-ICSS MII Timing
6.11.5.13.7.2.1
PRU-ICSS MII Timing Conditions
6.11.5.13.7.2.2
PRU-ICSS MII Timing Requirements - MII[x]_RX_CLK
382
6.11.5.13.7.2.3
PRU-ICSS MII Timing Requirements - MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER
384
6.11.5.13.7.2.4
PRU-ICSS MII Switching Characteristics - MII[x]_TX_CLK
386
6.11.5.13.7.2.5
PRU-ICSS MII Switching Characteristics - MII[x]_TXD[3:0] and MII[x]_TXEN
388
6.11.5.14
Sigma Delta Filter Module (SDFM)
6.11.5.14.1
SDFM Timing Conditions
6.11.5.14.2
SDFM Switching Characteristics
6.11.5.15
Universal Asynchronous Receiver/Transmitter (UART)
6.11.5.15.1
UART Timing Conditions
6.11.5.15.2
UART Timing Requirements
6.11.5.15.3
UART Switching Characteristics
396
6.11.6
Emulation and Debug
6.11.6.1
JTAG
6.11.6.1.1
JTAG Timing Conditions
6.11.6.1.2
JTAG Timing Requirements
6.11.6.1.3
JTAG Switching Characteristics
402
6.11.6.2
Trace
6.11.6.2.1
Debug Trace Timing Conditions
6.11.6.2.2
Debug Trace Switching Characteristics
406
6.12
Decoupling Capacitor Requirements
6.12.1
Decoupling Capacitor Requirements
7
Detailed Description
7.1
Overview
7.2
Processor Subsystems
7.2.1
Arm Cortex-R5F Subsystem
8
Applications, Implementation, and Layout
8.1
Device Connection and Layout Fundamentals
8.1.1
External Oscillator
8.1.2
JTAG, EMU, and TRACE
8.1.3
OSPI Connections for Flash in Package (ZCZ_F)
9
Device and Documentation Support
9.1
Device Nomenclature
9.1.1
Standard Package Symbolization
9.1.2
Device Naming Convention
9.2
Tools and Software
9.3
Documentation Support
9.4
Support Resources
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
ZCZ|324
MPBGA29A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sprsp81b_oa
Data Sheet
AM263Px Sitara™ Microcontrollers