With the current technology boom pushing the performance of ASICs, it is imperative that all aspects outside of the chip are carefully reviewed in order to ensure a successful product. These areas may include system power supply, clock distribution, board/backplane design, signal quality, and overall mixed signal performance across various types of media. The high performance ASICs of today's technology rely on vendor specialized IP like SERDES, SPI-4.2 and DDR interfaces. In order to ensure first pass success the System applications team is responsible for deploying EVM's (evaluation modules) with key IP in order for the customer to evaluate the validity of the technology and evaluate performance of current system architecture and any tradeoffs needed prior the customer's final silicon arriving.

Beyond enabling the customer with leading edge IP in the form of an EVM, the Systems applications team can provide support in the following areas Integration Issues/Concerns:

• DFT choices
• Connector Selection
• Line Card PWB stackup review
• Chip Decoupling review
• Backplane stackup review
• Board layout guidelines
• Refclk sources and clock distribution schemes
• Compliance Testing (FC1, FC2, XAUI, GE)
• Interoperability Testing

These are just a few examples of support provided. In addition, TI has a state of the art characterization lab with leading edge equipment to perform any type of system/chip analysis and is available to it's customers for system analysis/tradeoffs.