Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)

This application report compares two approaches for synchronous bus-system designs. The focus of the report is the comparison of a system using central-synchronous system clock (CSSC) with a system operated with a source-synchronous system clock (SSSC). The basic characteristics of lines, key factors that influence the bus line delay, and the impedance of bus lines are described. The theoretical advantages of an SSSC system over a CSSC system are based on a comparison of timing budget calculations. Theoretical results are confirmed by measurements, using the GTLP demonstration backplane. In the SSSC mode, the system-clock frequency is, with a clock frequency of 120 MHz, about 2.4 times higher than in the CSSC mode.