A New Synchronization Circuit for Power Converters

The synchronization of multiple PWM and PFC controllers is desirable for many reasons. The most common reason is that it keeps all the noise at one particular frequency and makes it easier to filter. The circuit described changes the slope of the ramp to lock the converter's switching frequency to an applied signal by a phase locked loop turning it into a voltage-controlled oscillator. Furthermore, this circuit is suited for PWM controllers that have internal timing capacitors, such as the UCC28510 family and the UCC38083 family or that have more than one function dependant on the ramp such as maximum duty cycle limiting. The circuit takes both the frequency of the converter and the frequency of the synchronization signal and mixes the two, resulting in a pulse width modulated signal that is changing at the beat frequency of the two signals. This signal is used to increase or decrease the current that is charging the timing capacitor forcing the frequency of the converter to match the incoming synchronization signal. This approach results in 1) Synchronization of converters where the timing capacitor is unavailable and there is no synchronization pin available; 2) Uniform ramp amplitude from unit to unit, therefore, stable voltage gain and current compensation; and 3) No distortion of the ramp which allows for maximum duty cycle limiting.