How to Calculate the Period Jitter from the SSCR for High-Speed ADCs

This document introduces a general formula to translate the phase noise of a clock source, rated via the Single Sideband to Carrier Ratio, to the cycle-to-cycle jitter of the oscillation period. The link allows to seamlessly aggregate the external clock source phase noise, usually given in dBc/Hz, to the phase stability figure of the on-chip clock synchronization circuitry, usually rated in ps-RMS. This permits in turn to evaluate their impact on the total aperture jitter of a sampling circuit, finally enabling the determination of the SNR for systems like, as shown in this document, an analog-to-digital converter. The validity of the relationship between the time- and frequency-domain figures of merit has been first tested on the phase-noise spectrum featured by bipolar and CMOS integrated VCOs; thereafter, the most popular case of PLL-based frequency synthesizers has been treated both by adopting time-to-amplitude conversion techniques, or dedicated phase-noise testing equipment. The optimal performance enabled by a state-of-the-art aperture jitter, optimized by making use of the formulas here proposed and rigorously quantified in 250fs, is demonstrated on Texas Instruments ADS5420, a high-speed 14b 65 MSPS ADC for 3G wireless infrastructure BTS applications