TMS320C6000 Enhanced DMA: Example Applications (Rev. A)

The enhanced direct memory access (EDMA) controller is the backbone of the two-level cache architecture for the TMS320C6000? DSPs. The EDMA performs: o cache servicing o host-port servicing o user-programmable data transfers Through proper configuration, EDMA channels can be set up to operate continuously without requiring CPU intervention or reprogramming. This allows the CPU to use its MIPS for data processing, while the EDMA handles data management in the background. Either 16 or 64 channels, plus a Quick DMA (QDMA) register set, are programmable to perform data transfers during CPU operation. EDMA channels and QDMA register sets are useful to transfer data to/from any location in the DSP?s memory map. All transfers are synchronized and each channel has a dedicated synchronization event. Note that QDMA transfers are synchronized by the CPU. Each requestor (L2 controller, EDMA channel, HPI) submits a transfer request to be processed by the EDMA. The requests are queued according to priority, with higher priority requests serviced first. Because of the EDMA?s structure, transfers requested through different queues (though submitted according to priority) can occur simultaneously. This maximizes the bandwidth available to data transfers and allows for efficient transferring of data without hindering the performance of the cache. EDMA channels are configured in a special on-chip parameter RAM (PaRAM), with the capacity for multiple transfers for a particular channel to be stored in linked-list fashion...