Using IBIS Models for Timing Analysis (Rev. A)

Today?s high-speed interfaces require strict timings and accurate system design. To achieve the necessary timings for a given system, input/output buffer information specification (IBIS) models must be used. These models accurately represent the device drivers under various process conditions. Board characteristics, such as impedance, loading, length, number of nodes, etc., affect how the device driver behaves. This application report discusses how to properly use IBIS models to attain accurate timing analysis for a given system. This report focuses on the use of SDRAM with a TMS320C6000™ DSP, but is applicable to all interfaces that have setup and hold parameters.