Using the Power Scaling Library (Rev. A)

Power consumption is a key concern for embedded system developers. By developing low-power solutions, developers can deliver products that have longer battery life. One technique that can be used to save power is frequency and voltage scaling of the processor.

Since the power consumption of a DSP is proportional to the system clock switching speed, running the device at the lowest possible frequency, while continuing to meet all of the application's timing requirements, can save power by minimizing the idle time. In addition, batteries have a non-linear discharge pattern, where higher currents drain the battery quicker. Thus, executing at lower frequencies can extend battery life. Since lower frequencies require less voltage, an even greater decrease in power consumption can be achieved if the voltage is also lowered when the frequency is lowered.

This application report describers the power scaling library (PSL) and how to use it in your own C55x applications.

Do note that this tooling currently supports the C5503, C5507, C5509A, and C5510 Rev 2.x silicon only.