TMS320C621x/TMS320C671x EDMA Architecture

The enhanced DMA (EDMA) controller of the TMS320C621x™/TMS320C671x™ device is a highly efficient data transfer engine. To maximize bandwidth, minimize transfer interference, and fully utilize the resources of the EDMA, it is crucial to understand the architecture of the engine. Transfer requests (TRs) originate from many requestors, including sixteen programmable EDMA channels, the level 2 (L2) memory controller, and master peripherals. The EDMA controls access to resources and arbitrates between concurrent transfers. Understanding the interaction points for transfer requests in the EDMA architecture is crucial to creating a system that takes full advantage of the EDMA?s capabilities.