Implementing Serial Rapid I/O PCB layout on a TMS320C6455 Hardware Design (Rev. A)

This application report contains implementation instructions for the Serial Rapid I/O (SRIO) interface on the TMS320C6455 DSP device. The approach to specifying interface timing and physical requirements for the SRIO interface is quite different than previous approaches for other interfaces.

Serial Rapid I/O is an industry-standard high-speed switched-packet interconnect. Physical layer data transmission utilizes analog serializer/deserializers (serdes) to feed low-output-swing differential CML buffers. Proper printed circuit board (PCB) design for this interface resembles analog or RF design, and is very different than traditional parallel digital bus design.

Due to this analog nature of SRIO, it is not possible to specify the interface in a traditional DSP digital interface manner. Furthermore, it is undesirable to specify the interface in terms of the raw physical requirements laid out by the SRIO specification. Understanding the SRIO specification and producing a compliant PCB based on the explicit and implicit requirements there demands significant time, experience, and expensive tools.

For the TMS320C6455 SRIO interface, the approach is to reduce the specification to a set of easy-to-follow PCB routing rules. TI has performed the simulation and system design work to ensure SRIO interface requirements are met. This document describes the content of this SRIO implementation.