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TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (Rev. B)

This document discusses the two-level internal memory used for program and data in the TMS320C621x/C671x digital signal processors (DSPs) of the TMS320C6000 DSP family. The first-level program cache is designated L1P and the first-level data cache is designated L1D. Both the program and data memory share the second-level memory, designated L2. L2 is configurable, allowing for various amounts of cache and SRAM.



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