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TMS320C64x DSP Two Level Internal Memory Reference Guide (Rev. C)

The TMS320C621x, TMS320C671x, and TMS320C64x digital signal processors (DSPs) of the TMS320C6000 DSP family have a two-level memory architecture for program and data. The first-level program cache is designated L1P, and the first-level data cache is designated L1D. Both the program and data memory share the second-level memory, designated L2. This document discusses the C64x DSP two-level internal memory.



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