TMS320C645x DSP Software-Programmable Phase-Locked Loop (PLL) Controller UG
This document describes the operation of the software-programmable phase-locked loop (PLL) controller in the TMS320C645x digital signal processors (DSPs). The PLL controller offers flexibility and convenience by way of software-configurable multipliers and dividers to modify the input signal internally. The resulting clock outputs are passed to the TMS320C645x DSP core, peripherals, and other modules inside the TMS320C645x DSP.
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