The SMJ320C80 is a multi-processor DSP. It integrates onto a single integrated circuit five powerful, fully programmable processors, a sophisticated DMA (direct memory access) controller with a DRAM, SRAM, and VRAM external memory interface, 50K bytes of SRAM, and video timing control. Of the 50K bytes of SRAM, 32K bytes are shared among the five processors to support various parallel-processing approaches. This unique combination of processing hardware facilitates a wide range of multimedia and other applications that require a large amount of processing.
Four of the five processors are identical, advanced digital signal processors (ADSPs) that have hardware to support multiply-intensive signal processing, bit-field-intensive pixel manipulations, and bit-field-intensive operations. Each of the ADSPs is capable of performing multiple RISC-equivalent (reduced instruction set computer) operations in a single cycle. The fifth processor, the master processor, is a 32-bit RISC CPU that includes a high-performance IEEE-754-compatible floating-point unit. You can program all five processors in both C and assembly language.
In addition to the fully programmable processors, the transfer controller (TC) is an intelligent DMA controller that manages all memory traffic. The TC performs packet transfers that move data between on- and off-chip memory. These packet transfers include instruction- and data-cache servicing, as well as complex programmable byte-aligned array transfers that can include X/Y or linear addressing of the source or destination array.
The 'C80 is capable of performing the equivalent of more than two billion RISC-like operations per second. In some applications, a single 'C80 can do the job of more than ten of the most powerful DSPs or general-purpose processors previously available. During each second of processing, it can move 2.4 Gbytes of data and 1.8 Gbytes of instructions within the chip, plus 400 Mbytes of data to off chip memory.
- Over two billion RISC-like operations per second
- Four 32-bit advanced DSPs in a multiple-instruction, multiple-data(MIMD) configuration
- A 32-bit RISC(reduced instruction set computer) master processor with an integrated IEEE-754 floating-point unit; optimized for programming in C
- Byte-addressable machine with big-endian and little-endian byte ordering support
- 50K bytes of on-chip SRAM
- On-chip crossbar that allows five instruction fetches and ten parallel data accesses per cycle
- 64-bit transfer controller capable of up to 400 Mbytes/s on- and off-chip memory transfers
- Dynamic bus sizing for 64, 32, 16, or 8 bits
- Access to 64-bit VRAM/DRAM/SRAM memory
- 4-Gbyte memory address space
- A video controller that contains dual frame timers for simultaneous image capture and display
- Four external interrupts, edge- and level-triggered
- Built-in emulation features accessed via an IEEE 1149.1 test port
- Full-scan design (plus boundary scan), accessed via an IEEE 1149.1 test port
- 3.3-volt processor
- TI EPIC 0.5-um CMOS technology
- Approximately 4 million transistors
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