Altium

Design Rule Verification Report

Date: 2/6/2020
Time: 5:54:13 PM
Elapsed Time: 00:00:34
Filename: C:\TI_Projects\RAP_Projects\radar\Cascade_EVM\MMWCAS-RF-EVM\RevC\Altium_Project\MMWCAS_RF_EVM_Bitbucket\Layout\PROC054D_MMWCAS_RF_EVM.PcbDoc
Warnings: 0
Rule Violations: 0
Waived Violations: 27

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=5mil) (InPoly and InLayerClass('Internal')),(isvia and (WithinRoom('Room1') or WithinRoom('Room2') or WithinRoom('Room3') or WithinRoom('Room4'))) 0
Clearance Constraint (Gap=21mil) (InAnyDifferentialPair and IsTrack),(Istrack and InLayerClass('Bottom')) 0
Clearance Constraint (Gap=200mil) (InLayerClass('L3') and InPoly),((isarc or istrack) AND InNetClass('FMCW')) 0
Clearance Constraint (Gap=1mil) (IsKeepOut),(All) 0
Clearance Constraint (Gap=9mil) ((WithinRoom('GND_Rule1') or WithinRoom('GND_Rule2') or WithinRoom('GND_Rule3') or WithinRoom('GND_Rule4')) and IsPad),(InPoly) 0
Clearance Constraint (Gap=8mil) (InNetClass('FMCW') and (istrack or IsArc) and InLayerClass('L3')),(IsVia and (WithinRoom('A1') or WithinRoom('A2') or WithinRoom('A3') or WithinRoom('A4') or WithinRoom('A5') or WithinRoom('A6') or WithinRoom('A7') or WithinRoom('A8') or WithinRoom('A9'))) 0
Clearance Constraint (Gap=7mil) (IsRegion and InNetClass('20GHz')),(InPoly and InNet('GND')) 0
Clearance Constraint (Gap=7mil) (InLayerClass('Top') and All and (WithinRoom('Room5') or WithinRoom('Room6'))),(All) 0
Clearance Constraint (Gap=16mil) (InAnyDifferentialPair and IsTrack),(Istrack and InLayerClass('L6')) 0
Clearance Constraint (Gap=8mil) (isvia and InNetClass('FMCW') and (WithinRoom('Room5') OR WithinRoom('Room6'))),(InNet('GND') and InLayerClass('Top') and InPoly) 0
Clearance Constraint (Gap=21mil) (istrack and (InNetClass('12XX_CLOCK') or InNetClass('12XX_SYNC'))),(InLayerClass('L6') and inpoly) 0
Clearance Constraint (Gap=15.3mil) (istrack and (InNetClass('12XX_CLOCK') or InNetClass('12XX_SYNC'))),(InLayerClass('L3') and inpoly) 0
Clearance Constraint (Gap=4mil) ((InNetClass('TX') or InNetClass('RX')) and (istrack or IsArc or IsRegion)),(isvia) 0
Clearance Constraint (Gap=23.5mil) (istrack and (InNetClass('12XX_CLOCK') or InNetClass('12XX_SYNC'))),(InLayerClass('Bottom') and inpoly and not InNet('GND')) 0
Clearance Constraint (Gap=50mil) (InNetClass('FMCW') and (istrack or IsArc) and InLayerClass('L3')),(All) 0
Clearance Constraint (Gap=10mil) (All),(InPolygon) 0
Clearance Constraint (Gap=10mil) (InNetClass('Antenna')),(InPoly and InNet('GND') and InLayerClass('Top')) 0
Clearance Constraint (Gap=5mil) (All),(All) 0
Clearance Constraint (Gap=4mil) ((WithinRoom('Room1') or WithinRoom('Room2') or WithinRoom('Room3') or WithinRoom('Room4')) and All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=4mil) (Max=50mil) (Preferred=10mil) (All) 0
Routing Layers(All) 0
Routing Via (MinHoleWidth=5.8mil) (MaxHoleWidth=28mil) (PreferredHoleWidth=28mil) (MinWidth=15mil) (MaxWidth=50mil) (PreferedWidth=50mil) (All) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=5.5mil) (Max=10mil) (Prefered=7mil) and Width Constraints (Min=4mil) (Max=15mil) (Prefered=15mil) (All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=7.5mil) (All) 0
Minimum Annular Ring (Minimum=3.9mil) (IsVia) 0
Acute Angle Constraint [Tracks Only] (Minimum=40.000) (All) 0
Hole Size Constraint (Min=5.9mil) (Max=200mil) (All) 0
Pads and Vias to follow the Drill pairs settings 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=4mil) (All),(All) 0
Silk To Solder Mask (Clearance=3mil) (IsPad),(All) 0
Silk to Silk (Clearance=3mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Board Clearance Constraint (Gap=0mil) (All) 0
Component Clearance Constraint ( Horizontal Gap = 10mil, Vertical Gap = 10mil ) (All),(All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total 0

Waived Violations Count
Clearance Constraint (Gap=21mil) (InAnyDifferentialPair and IsTrack),(Istrack and InLayerClass('Bottom')) 4
Silk To Solder Mask (Clearance=3mil) (IsPad),(All) 23
Total 27

Rule Violations

Waived Violations

Clearance Constraint (Gap=21mil) (InAnyDifferentialPair and IsTrack),(Istrack and InLayerClass('Bottom'))
Clearance Constraint: (20.75mil < 21mil) Between Track (2195.999mil,2553.116mil)(2195.999mil,2664.88mil) on L8 BOTTOM And Track (2221.999mil,2625.88mil)(2234.999mil,2612.88mil) on L8 BOTTOM
Waived by at 8/17/2018 8:04:47 AM
Waive
Clearance Constraint: (17.31mil < 21mil) Between Track (2314.999mil,2502.701mil)(2314.999mil,2593.48mil) on L8 BOTTOM And Track (2337.559mil,2557.88mil)(2361.154mil,2534.285mil) on L8 BOTTOM
Waived by at 8/20/2018 9:51:55 AM
Waive
Clearance Constraint: (20.75mil < 21mil) Between Track (4513.999mil,1970.54mil)(4513.999mil,2571.001mil) on L8 BOTTOM And Track (4539.999mil,2532.001mil)(4552.999mil,2519.001mil) on L8 BOTTOM
Waived by at 8/17/2018 8:04:47 AM
Waive
Clearance Constraint: (18.31mil < 21mil) Between Track (4631.999mil,1917.289mil)(4631.999mil,2499.601mil) on L8 BOTTOM And Track (4655.559mil,2464.001mil)(4670.559mil,2449.001mil) on L8 BOTTOM
Waived by at 8/17/2018 8:04:47 AM
Waive
Back to top

Silk To Solder Mask (Clearance=3mil) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (1.262mil < 3mil) Between Arc (2532.666mil,2653.276mil) on Top Overlay And Pad C168-2(2518.305mil,2631.895mil) on L1 TOP [Top Overlay] to [Top Solder] clearance [1.262mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.843mil < 3mil) Between Pad C100-1(5534.172mil,809.766mil) on L1 TOP And Track (5513.537mil,791.422mil)(5553.537mil,791.422mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [2.843mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.843mil < 3mil) Between Pad C105-1(5374.353mil,809.766mil) on L1 TOP And Track (5354.989mil,791.422mil)(5394.989mil,791.422mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [2.843mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.843mil < 3mil) Between Pad C112-1(5534.172mil,1140.447mil) on L1 TOP And Track (5513.537mil,1158.79mil)(5553.537mil,1158.79mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [2.843mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.843mil < 3mil) Between Pad C117-1(5374.353mil,1140.447mil) on L1 TOP And Track (5354.989mil,1158.79mil)(5394.989mil,1158.79mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [2.843mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (1.416mil < 3mil) Between Pad C121-2(5050.257mil,956.888mil) on L8 BOTTOM And Track (5033.803mil,940.065mil)(5056.803mil,940.065mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [1.416mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.843mil < 3mil) Between Pad C42-1(663.448mil,1597.621mil) on L1 TOP And Track (642.812mil,1579.278mil)(682.812mil,1579.278mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [2.843mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.843mil < 3mil) Between Pad C47-1(503.628mil,1597.621mil) on L1 TOP And Track (484.264mil,1579.278mil)(524.264mil,1579.278mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [2.843mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.843mil < 3mil) Between Pad C54-1(663.448mil,1928.302mil) on L1 TOP And Track (642.812mil,1946.646mil)(682.812mil,1946.646mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [2.843mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.843mil < 3mil) Between Pad C59-1(503.628mil,1928.302mil) on L1 TOP And Track (484.264mil,1946.646mil)(524.264mil,1946.646mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [2.843mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.081mil < 3mil) Between Pad R44-1(185.281mil,1783.208mil) on L8 BOTTOM And Track (167.187mil,1806.288mil)(190.187mil,1806.288mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [2.081mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.081mil < 3mil) Between Pad R44-2(245.281mil,1783.208mil) on L8 BOTTOM And Track (240.187mil,1806.288mil)(263.187mil,1806.288mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [2.081mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.081mil < 3mil) Between Pad R68-1(5056.005mil,1000.352mil) on L8 BOTTOM And Track (5037.911mil,1023.433mil)(5060.911mil,1023.433mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [2.081mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.081mil < 3mil) Between Pad R68-2(5116.005mil,1000.352mil) on L8 BOTTOM And Track (5110.911mil,1023.433mil)(5133.911mil,1023.433mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [2.081mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (0.956mil < 3mil) Between Pad U10-4(4118.78mil,3096.82mil) on L8 BOTTOM And Track (4076.965mil,3114.207mil)(4117.965mil,3114.207mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.956mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.567mil < 3mil) Between Pad U10-4(4118.78mil,3096.82mil) on L8 BOTTOM And Track (4117.965mil,3114.207mil)(4117.965mil,3137.207mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [2.567mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.568mil < 3mil) Between Pad U10-4(4118.78mil,3096.82mil) on L8 BOTTOM And Track (4117.965mil,3114.207mil)(4117.965mil,3137.207mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [2.568mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.567mil < 3mil) Between Pad U10-4(4118.78mil,3096.82mil) on L8 BOTTOM And Track (4117.965mil,3114.207mil)(4158.965mil,3114.207mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [2.567mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (0.956mil < 3mil) Between Pad U10-5(4138.465mil,3096.82mil) on L8 BOTTOM And Track (4117.965mil,3114.207mil)(4158.965mil,3114.207mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.956mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (0.956mil < 3mil) Between Pad U10-6(4158.15mil,3096.82mil) on L8 BOTTOM And Track (4117.965mil,3114.207mil)(4158.965mil,3114.207mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.956mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.853mil < 3mil) Between Pad U10-6(4158.15mil,3096.82mil) on L8 BOTTOM And Track (4158.965mil,3114.207mil)(4158.965mil,3137.207mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [2.853mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.853mil < 3mil) Between Pad U10-6(4158.15mil,3096.82mil) on L8 BOTTOM And Track (4158.965mil,3114.207mil)(4158.965mil,3137.207mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [2.853mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Silk To Solder Mask Clearance Constraint: (2.853mil < 3mil) Between Pad U10-6(4158.15mil,3096.82mil) on L8 BOTTOM And Track (4158.965mil,3114.207mil)(4199.965mil,3114.207mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [2.853mil]
Waived by at 8/29/2018 3:45:18 AM
Component outline can be ignored
Back to top