Altiumcustomize

Design Rule Verification Report

Date : 6/12/2015
Time : 5:11:01 PM
Elapsed Time : 00:00:07
Filename : D:\Avinash\TIDA-00368\FINAL DATABASE TIDA-00368_E2\TIDA-00368_E2.PcbDoc
Warnings : 0
Rule Violations : 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=15mil) (OnCopper and InPolygon),(IsKeepOut) 0
Clearance Constraint (Gap=8mil) (IsVia),(IsThruPin) 0
Clearance Constraint (Gap=40mil) (InPadClass('MTG')),(InPolygon) 0
Clearance Constraint (Gap=15mil) (InPolygon),(All) 0
Clearance Constraint (Gap=25mil) (InPolygon),(InPolygon) 0
Clearance Constraint (Gap=8mil) (IsSMTPin),(IsVia) 0
Net Antennae (Tolerance=0mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Hole Size Constraint (Min=7mil) (Max=251mil) (All) 0
Minimum Annular Ring (Minimum=5mil) (All) 0
Minimum Annular Ring (Minimum=5.905mil) (IsVia and InAnyComponent) 0
Un-Routed Net Constraint ( (All) ) 0
Routing Via (MinHoleWidth=12mil) (MaxHoleWidth=16mil) (PreferredHoleWidth=12mil) (MinWidth=24mil) (MaxWidth=32mil) (PreferedWidth=24mil) (All) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=12mil) (PreferredHoleWidth=8mil) (MinWidth=19mil) (MaxWidth=24mil) (PreferedWidth=20mil) (IsVia and InAnyComponent) 0
Routing Layers(All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Width Constraint (Min=8mil) (Max=100mil) (Preferred=10mil) (All) 0
Clearance Constraint (Gap=8mil) (All),(All) 0
Width Constraint (Min=8mil) (Max=100mil) (Preferred=20mil) (InNetClass('POWER')) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=16mil) (PreferredHoleWidth=16mil) (MinWidth=19.685mil) (MaxWidth=32mil) (PreferedWidth=32mil) (InNetClass('POWER')) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Clearance Constraint (Gap=7.8mil) (InPadClass('U8')),(All) 0
Total 0