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0 Delay PLL

TI analog 0 Delay PLL Clocks and Timers products are a subset of analog Clock Distribution solutions. This page is your resource to download datasheets, application notes, order samples and use parametric search to research other Clocks and Timers-related analog solutions.

Application Notes   

  • DDR2 Memory Interface Clocks and Registers - Overview (scaa101.HTM, 8 KB)
    25 Mar 2009 Abstract
  • Application Examples for CDCUx877x PLL family (scaa087.HTM, 8 KB)
    07 May 2008 Abstract
 

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Buffer/Driver (33)
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No. of Outputs Output Level Operating Frequency Range (min) (MHz) t(phase error) (min) (ps) Operating Frequency Range (max) (MHz) VCC (V) Absolute Jitter (cycle-to-cycle) (ps) Input Level Output Drive (mA) Static Current (mA) t(phase error) (max) (ps) tsk(o) (ns) Pin/Package Operating Temp Range (Celsius)
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Part Number  Status  
Sub Family  		No. of Outputs  Output Level  Operating Frequency Range (min) (MHz)  t(phase error) (min) (ps)  Operating Frequency Range (max) (MHz)  VCC (V)  Absolute Jitter (cycle-to-cycle) (ps)  Input Level  Output Drive (mA)  Static Current (mA)  t(phase error) (max) (ps)  tsk(o) (ns)  Buffer/Driver  Spread Spectrum Clocking (SSC)  Pin/Package  Approx. Price (US$)  
Description  
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CDC857-2ACTIVE  Differential Ended  10  SSTL-2  66  -150  167  3.3/2.5  75  LVTTL  
SSTL-2  		    150  0.100  Yes  Yes  48TSSOP8.30 | 1ku  Phase-Lock Loop Clock Drivers  
CDCU2A877ACTIVE  Differential Ended  10  SSTL-18  125  -35  410  1.8  30  SSTL-18  18  0.5  35  0.03  Yes  Yes  52BGA MICROSTAR JUNIOR3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver with high output drive for DDR2 SDRAM Applications  
CDCU877ACTIVE  Differential Ended  10  SSTL-18  10  -50  400  1.8  30  SSTL-18  9  0.5  50  0.035  Yes  Yes  40QFN
52BGA MICROSTAR JUNIOR		3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications  
CDCU877AACTIVE  Differential Ended  10  SSTL-18  10  -50  400  1.8  30  SSTL-18  9  0.5  50  0.035  Yes  Yes  40QFN
52BGA MICROSTAR JUNIOR		3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications  
CDCU877BACTIVE  Differential Ended  10  SSTL-18  10  -50  340  1.8  30  SSTL-18  9  0.5  50  0.035      52BGA MICROSTAR JUNIOR3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications  
CDCUA877ACTIVE  Differential Ended  10  SSTL-18  125  -35  410  1.8  30  SSTL-18  9  0.5  35  0.03  Yes  Yes  52BGA MICROSTAR JUNIOR3.35 | 1ku  1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications  
CDCV850ACTIVE  Differential Ended  10  SSTL-2  60  -120  140  2.5  30  LVTTL  
SSTL-2  		    120  0.075  Yes  Yes  48TSSOP2.05 | 1ku  2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface  
CDCV855ACTIVE  Differential Ended  4  SSTL-2  60  -100  180  2.5  50  SSTL-2      100  0.050  Yes  Yes  28TSSOP1.15 | 1ku  1:4 DDR PLL Clock Driver  
CDCV857ACTIVE  Differential Ended  10  SSTL-2  60  -100  200  2.5  75  LVTTL  
SSTL-2  		    100  0.075  Yes  Yes  48TSSOP3.90 | 1ku  1:10 DDR Phase-Lock Loop Clock Driver  
CDCV857AACTIVE  Differential Ended  10  SSTL-2  60  100  180  2.5  50  SSTL-2      100  0.075  Yes  Yes  48TSSOP
56BGA MICROSTAR JUNIOR		2.90 | 1ku  2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications  
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