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HPA Clock Generators

Application Notes   

  • A General Guideline: How to Use the CDCF5801A for Phase Alignment/Adjustment (Rev. B) (scaa070b.HTM, 8 KB)
    21 Oct 2005 Abstract
  • Using Configurable Active Delay Elements in CDCF5801A Feedback Loop (scaa075.HTM, 8 KB)
    15 Sep 2004 Abstract
 

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2 Results    

Part Number  Status  VCC (V)  Input Level  Jitter-Peak to Peak(P-P) or Cycle to Cycle(C-C)  Divider Ratio  Output Level  Temp Range (C)  Multiplier Ratio  Output Frequency (min) (Mhz)  Output Frequency (max) (Mhz)  3.3V Vcc / Vdd  Multiplier/Divider  Spread Spectrum Clocking (SSC)  Pin/Package  Approx. Price (US$)  
Description  
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CDC5801AACTIVE  3.3  LVCMOS  
LVTTL  		P-P PA bypassed=40ps, PA active=70ps, Division mode=75ps  2  
3  
4  		LVDS  
LVPECL  
LVTTL  		S(-40 to 85)  4  
6  
8  		150  500        24SSOP/QSOP3.70 | 1ku  Low Jitter Clock Multiplier & Divider w/Programmable Delay & Phase Alignment  
CDCF5801AACTIVE  3.3  HSTL  
LVPECL  
LVTTL  		P-P 120ps(25 to 200 MHz), C-C +/- 70 (25 to 200MHz)    LVDS  
LVPECL  
LVTTL  		S(-40 to 85)  1  
2  
4  
8  		    Yes  Yes  Yes  24SSOP/QSOP2.95 | 1ku  Low Jitter PLL Based Multiplier/Divider with programmable delay lines down to sub 10ps  
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2 Results