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Differential Ended

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  • DDR2 Memory Interface Clocks and Registers - Overview (scaa101.HTM, 8 KB)
    25 Mar 2009 Abstract
  • Application Examples for CDCUx877x PLL family (scaa087.HTM, 8 KB)
    07 May 2008 Abstract
 

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13 Results  
Buffer/Driver (12) 1.8V Vcc/Vdd (3) Spread Spectrum Clocking (SSC) (12)
2.5V - 3.3V Vcc / Vdd (1) spacer 2.5V Vcc/Vdd (7) spacer
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VCC (V) No. of Outputs Operating Frequency Range (max) (MHz) Output Level Input Level
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13 Results - Show All Results 1 - 10 of 13 Results |  Next >Page  1 | 2  

Part Number  Status  VCC (V)  No. of Outputs  Operating Frequency Range (max) (MHz)  Output Level  Buffer/Driver  2.5V - 3.3V Vcc / Vdd  1.8V Vcc/Vdd  2.5V Vcc/Vdd  Input Level  Spread Spectrum Clocking (SSC)  Absolute Jitter (cycle-to-cycle) (ps)  tsk(o) (ns)  Pin/Package  Approx. Price (US$)  
Description  
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CDC857-2ACTIVE  3.3/2.5  10  167  SSTL-2  Yes  Yes      LVTTL  
SSTL-2  		Yes  75  0.100  48TSSOP8.30 | 1ku  Phase-Lock Loop Clock Drivers  
CDCU2A877ACTIVE  1.8  10  410  SSTL-18  Yes    Yes    SSTL-18  Yes  30  0.03  52BGA MICROSTAR JUNIOR3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver with high output drive for DDR2 SDRAM Applications  
CDCU877ACTIVE  1.8  10  400  SSTL-18  Yes    Yes    SSTL-18  Yes  30  0.035  40QFN
52BGA MICROSTAR JUNIOR		3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications  
CDCU877AACTIVE  1.8  10  400  SSTL-18  Yes        SSTL-18  Yes  30  0.035  40QFN
52BGA MICROSTAR JUNIOR		3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications  
CDCU877BACTIVE  1.8  10  340  SSTL-18          SSTL-18    30  0.035  52BGA MICROSTAR JUNIOR3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications  
CDCUA877ACTIVE  1.8  10  410  SSTL-18  Yes    Yes    SSTL-18  Yes  30  0.03  52BGA MICROSTAR JUNIOR3.35 | 1ku  1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications  
CDCV850ACTIVE  2.5  10  140  SSTL-2  Yes      Yes  LVTTL  
SSTL-2  		Yes  30  0.075  48TSSOP2.05 | 1ku  2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface  
CDCV855ACTIVE  2.5  4  180  SSTL-2  Yes      Yes  SSTL-2  Yes  50  0.050  28TSSOP1.15 | 1ku  1:4 DDR PLL Clock Driver  
CDCV857ACTIVE  2.5  10  200  SSTL-2  Yes      Yes  LVTTL  
SSTL-2  		Yes  75  0.075  48TSSOP3.90 | 1ku  1:10 DDR Phase-Lock Loop Clock Driver  
CDCV857AACTIVE  2.5  10  180  SSTL-2  Yes      Yes  SSTL-2  Yes  50  0.075  48TSSOP
56BGA MICROSTAR JUNIOR		2.90 | 1ku  2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications  
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13 Results - Show All Results 1 - 10 of 13 Results |  Next >Page  1 | 2