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External VCXO Output

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HPA Clock Generators

Application Notes   

  • TLK313x/CDCM7005 Multi-hop Performance (slla296.HTM, 8 KB)
    01 Nov 2009 Abstract
  • Using The CDC7005 as a 1:5 PECL Buffer w/Programmable Divider Ratio (Rev. A) (scaa060a.HTM, 8 KB)
    29 May 2009 Abstract
 

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No. of Outputs Output Frequency (min) (Mhz) Output Frequency (max) (Mhz) Output Level Input Level
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4 Results    

Part Number  Status  VCC (V)  No. of Outputs  Temp Range (C)  Output Frequency (min) (Mhz)  Output Frequency (max) (Mhz)  Output Level  Input Level  Jitter Cleaner  Pin/Package  Approx. Price (US$)  
Description  
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CDC7005ACTIVE  3.3  5  S(-40 to 85)  10  800  LVPECL  LVCMOS  
LVPECL  		Yes  48QFN
64BGA		10.00 | 1ku  High Performance, Low Phase Noise, Low Skew Clock Synchronizer that Synchronizes Ref Clock to VCXO  
CDCE72010ACTIVE  3.3  10    0.001  1500  LVCMOS  
LVDS  
LVPECL  		LVCMOS  
LVPECL  		Yes  64VQFN10.95 | 1ku  10 Outputs Low Jitter Clock Synchronizer and Jitter Cleaner  
CDCM7005ACTIVE  3.3  5      1500  LVCMOS  
LVPECL  		LVCMOS (REF_CLK)  
LVPECL (VCXO_CLK)  		Yes  48QFN
64BGA		9.50 | 1ku  High Performance, Low Phase Noise, Low Skew Clock Synchronizer that Synchronizes Ref Clock to VCXO  
CDCM7005-SPNEW/
ACTIVE  		3.3  5      1500  LVCMOS  
LVPECL  		LVCMOS (REF_CLK)  
LVPECL (VCXO_CLK)  		Yes  52CFP2272.80 | 1ku  3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer And Jitter Cleaner  
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4 Results