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Application Notes   

  • Design Considerations for TI's CDCV857/CDCV857A/CDCV855 DRR PLL (Rev. A) (scaa054a.HTM, 8 KB)
    20 Nov 2005 Abstract
  • Design Considerations for TI's CDCV857/CDCV857A DRR PLL (scaa054.HTM, 8 KB)
    10 Jan 2002 Abstract
 

You've Selected: DDR PLL
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5 Results    

Part Number  Status  VCC (V)  Absolute Jitter (cycle-to-cycle) (ps)  No. of Outputs  tsk(o) (ns)  t(phase error) (min) (ps)  t(phase error) (max) (ps)  Input Level  Output Level  Operating Frequency Range (min) (MHz)  Operating Frequency Range (max) (MHz)  Buffer/Driver  2.5V Vcc/Vdd  Spread Spectrum Clocking (SSC)  Pin/Package  Approx. Price (US$)  
Description  
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CDCV850ACTIVE  2.5  30  10  0.075  -120  120  LVTTL  
SSTL-2  		SSTL-2  60  140  Yes  Yes  Yes  48TSSOP2.05 | 1ku  2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface  
CDCV855ACTIVE  2.5  50  4  0.050  -100  100  SSTL-2  SSTL-2  60  180  Yes  Yes  Yes  28TSSOP1.15 | 1ku  1:4 DDR PLL Clock Driver  
CDCV857ACTIVE  2.5  75  10  0.075  -100  100  LVTTL  
SSTL-2  		SSTL-2  60  200  Yes  Yes  Yes  48TSSOP3.90 | 1ku  1:10 DDR Phase-Lock Loop Clock Driver  
CDCV857AACTIVE  2.5  50  10  0.075  100  100  SSTL-2  SSTL-2  60  180  Yes  Yes  Yes  48TSSOP
56BGA MICROSTAR JUNIOR		2.90 | 1ku  2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications  
CDCV857BACTIVE  2.5  50  10  0.100  100  100  SSTL-2  SSTL-2  60  200  Yes  Yes  Yes  48TSSOP
56BGA MICROSTAR JUNIOR		3.65 | 1ku  2.5 V Phase Lock Loop DDR Clock Driver  
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5 Results