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Application Notes   

  • DDR2 Memory Interface Clocks and Registers - Overview (scaa101.HTM, 8 KB)
    25 Mar 2009 Abstract
  • Application Examples for CDCUx877x PLL family (scaa087.HTM, 8 KB)
    07 May 2008 Abstract
 

You've Selected: DDR2 PLL
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5 Results    

Part Number  Status  VCC (V)  No. of Outputs  Output Drive (mA)  Output Level  Static Current (mA)  Operating Frequency Range (min) (MHz)  t(phase error) (min) (ps)  Absolute Jitter (cycle-to-cycle) (ps)  Operating Frequency Range (max) (MHz)  tsk(o) (ns)  t(phase error) (max) (ps)  Input Level  Numeric Price for Sort  Buffer/Driver  1.8V Vcc/Vdd  Spread Spectrum Clocking (SSC)  Pin/Package  Approx. Price (US$)  
Description  
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CDCU2A877ACTIVE  1.8  10  18  SSTL-18  0.5  125  -35  30  410  0.03  35  SSTL-18  3.05  Yes  Yes  Yes  52BGA MICROSTAR JUNIOR3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver with high output drive for DDR2 SDRAM Applications  
CDCU877ACTIVE  1.8  10  9  SSTL-18  0.5  10  -50  30  400  0.035  50  SSTL-18  3.05  Yes  Yes  Yes  40QFN
52BGA MICROSTAR JUNIOR		3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications  
CDCU877AACTIVE  1.8  10  9  SSTL-18  0.5  10  -50  30  400  0.035  50  SSTL-18  3.05  Yes    Yes  40QFN
52BGA MICROSTAR JUNIOR		3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications  
CDCU877BACTIVE  1.8  10  9  SSTL-18  0.5  10  -50  30  340  0.035  50  SSTL-18  3.05        52BGA MICROSTAR JUNIOR3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications  
CDCUA877ACTIVE  1.8  10  9  SSTL-18  0.5  125  -35  30  410  0.03  35  SSTL-18  3.35  Yes  Yes  Yes  52BGA MICROSTAR JUNIOR3.35 | 1ku  1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications  
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5 Results