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SN74SSQEA32882 : JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test

Application Notes   

  • DDR3 Register Input Bus Termination Measurement (scaa107.HTM, 9 KB)
    16 Nov 2009 Abstract
  • CMR Programming for DDR3 Registers (scaa102.HTM, 8 KB)
    25 Jun 2009 Abstract
 

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2 Results    

Part Number  Status  VCC (V)  Absolute Jitter (cycle-to-cycle) (ps)  Operating Frequency Range (min) (MHz)  Operating Frequency Range (max) (MHz)  t(phase error) (max) (ps)  Input Level  No. of Outputs  Buffer/Driver  Spread Spectrum Clocking (SSC)  Pin/Package  Approx. Price (US$)  
Description  
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SN74SSQE32882ACTIVE  1.425 to 1.575  40  300  670  50  SSTL_15  60  Yes  Yes  176BGA5.90 | 1ku  JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test  
SN74SSQEA32882NEW
ACTIVE  		1.35  
1.5  		40  300  810    SSTL_15  60  Yes    176BGA6.20 | 1ku  JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test  
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2 Results