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Analog eLAB ™

TRX ADC/DAC Frequency Synthesizers/Jitter Cleaners

HPA Clock Generators
  • Q3 2009 Issue Analog Applications Journal (slyt337.PDF, 2 MB)
    14 Jul 2009 Download
  • Impact of sampling-clock spurs on ADC performance (slyt338.PDF, 1.13 MB)
    14 Jul 2009 Download
 

You've Selected: TRX ADC/DAC Frequency Synthesizers/Jitter Cleaners


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7 Results  
Jitter Cleaner (2) 3.3V Vcc / Vdd (2)
Multiplier/Divider (1) spacer Integrated EEPROM (2) spacer
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VCC (V) Input Level Divider Ratio Output Frequency (min) (Mhz) Output Frequency (max) (Mhz) Output Level Pin/Package
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7 Results    

Part Number  Status  VCC (V)  Input Level  Divider Ratio  Output Frequency (min) (Mhz)  Output Frequency (max) (Mhz)  Jitter Cleaner  Output Level  Multiplier/Divider  3.3V Vcc / Vdd  Integrated EEPROM  Pin/Package  Approx. Price (US$)  
Description  
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CDCE72010ACTIVE  3.3  LVCMOS  
LVPECL  
1 - 80  0.001  1500  Yes  LVCMOS  
LVDS  
LVPECL  
Yes  Yes  Yes  64VQFN10.95 | 1ku  10 Outputs Low Jitter Clock Synchronizer and Jitter Cleaner  
CDCE18005ACTIVE  3.3  LVCMOS  
LVDS  
LVPECL  
       LVCMOS  
LVDS  
LVPECL  
 Yes    48QFN6.00 | 1ku  5/10 Outputs Clock Buffer with Divider  
CDCM7005ACTIVE  3.3  LVCMOS (REF_CLK)  
LVPECL (VCXO_CLK)  
1  
16  
2  
3  
4  
6  
8  
 1500  Yes  LVCMOS  
LVPECL  
     48QFN
64BGA
9.50 | 1ku  High Performance, Low Phase Noise, Low Skew Clock Synchronizer that Synchronizes Ref Clock to VCXO  
CDCLVP215ACTIVE  2.5, 3.3  LVPECL          LVPECL        32QFN5.55 | 1ku  Dual 1:5 High Speed LVPECL Fan Out Buffer  
CDCLVP110ACTIVE  2.5, 3.3  HSTL, LVPECL          LVPECL        32LQFP5.55 | 1ku  1:10 LVPECL/HSTL to LVPECL Clock Driver  
CDCLVD110AACTIVE  2.5  LVDS          LVDS        32LQFP
32QFN
5.90 | 1ku  1-to-10 LVDS Clock Buffer up to 1100MHz with Minimum Skew for Clock Distribution  
CDCE62005ACTIVE  3.3  LVCMOS  
LVDS  
LVPECL  
Universal  4.25  1175    LVCMOS  
LVDS  
LVPECL  
   Yes  48QFN7.50 | 1ku  5/10 Outputs Clock Generator/Jitter Cleaner with Integrated Dual VCO  
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7 Results