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SN74SSQEA32882 : JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test

Application Notes   

  • DDR3 Register Input Bus Termination Measurement (scaa107.HTM, 9 KB)
    16 Nov 2009 Abstract
  • CMR Programming for DDR3 Registers (scaa102.HTM, 8 KB)
    25 Jun 2009 Abstract
 

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   Memory Interface Clocks and Registers

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No. of Outputs Output Drive (mA) Vcc range (V) Output Level
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Part Number  Status  
Sub Family  		No. of Outputs  Output Drive (mA)  Vcc range (V)  Output Level  Numeric Price for Sort  Operating Frequency Range (max) (MHz)  t(phase error) (max) (ps)  Absolute Jitter (cycle-to-cycle) (ps)  tsk(o) (ns)  Static Current (mA)  VCC (V)  Input Level  Operating Frequency Range (min) (MHz)  t(phase error) (min) (ps)  Buffer/Driver  Spread Spectrum Clocking (SSC)  Pin/Package  Approx. Price (US$)  
Description  
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CDCV850ACTIVE  DDR PLL  10      SSTL-2  2.05  140  120  30  0.075    2.5  LVTTL  
SSTL-2  		60  -120  Yes  Yes  48TSSOP2.05 | 1ku  2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface  
CDCV855ACTIVE  DDR PLL  4      SSTL-2  1.15  180  100  50  0.050    2.5  SSTL-2  60  -100  Yes  Yes  28TSSOP1.15 | 1ku  1:4 DDR PLL Clock Driver  
CDCV857ACTIVE  DDR PLL  10      SSTL-2  3.9  200  100  75  0.075    2.5  LVTTL  
SSTL-2  		60  -100  Yes  Yes  48TSSOP3.90 | 1ku  1:10 DDR Phase-Lock Loop Clock Driver  
CDCV857AACTIVE  DDR PLL  10      SSTL-2  2.9  180  100  50  0.075    2.5  SSTL-2  60  100  Yes  Yes  48TSSOP
56BGA MICROSTAR JUNIOR		2.90 | 1ku  2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications  
CDCV857BACTIVE  DDR PLL  10      SSTL-2  3.65  200  100  50  0.100    2.5  SSTL-2  60  100  Yes  Yes  48TSSOP
56BGA MICROSTAR JUNIOR		3.65 | 1ku  2.5 V Phase Lock Loop DDR Clock Driver  
SN74SSTVF32852ACTIVE  DDR Register  48  -8/8  2.3 to 2.7  SSTL_2  6.35              SSTL_2          114BGA MICROSTAR
114LFBGA		6.35 | 1ku  24-Bit to 48-Bit Registered Buffer with SSTL_2 Inputs and Outputs  
CDCU2A877ACTIVE  DDR2 PLL  10  18    SSTL-18  3.05  410  35  30  0.03  0.5  1.8  SSTL-18  125  -35  Yes  Yes  52BGA MICROSTAR JUNIOR3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver with high output drive for DDR2 SDRAM Applications  
CDCU877ACTIVE  DDR2 PLL  10  9    SSTL-18  3.05  400  50  30  0.035  0.5  1.8  SSTL-18  10  -50  Yes  Yes  40QFN
52BGA MICROSTAR JUNIOR		3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications  
CDCU877AACTIVE  DDR2 PLL  10  9    SSTL-18  3.05  400  50  30  0.035  0.5  1.8  SSTL-18  10  -50  Yes  Yes  40QFN
52BGA MICROSTAR JUNIOR		3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications  
CDCU877BACTIVE  DDR2 PLL  10  9    SSTL-18  3.05  340  50  30  0.035  0.5  1.8  SSTL-18  10  -50      52BGA MICROSTAR JUNIOR3.05 | 1ku  1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications  
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