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ADC32RF52

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Dual channel 14-bit 1.5-GSPS ADC high SNR

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Data sheet

ADC32RF52

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Data sheet Order now

Product details

Sample rate (max) (Msps) 1500 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 2300 Features High Dynamic Range, High Performance, Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.1 Power consumption (typ) (mW) 2500 SNR (dB) 69.2 ENOB (bit) 10.5 SFDR (dB) 75 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 1500 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 2300 Features High Dynamic Range, High Performance, Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.1 Power consumption (typ) (mW) 2500 SNR (dB) 69.2 ENOB (bit) 10.5 SFDR (dB) 75 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RTD) 64 81 mm² 9 x 9
  • 14-Bit, dual channel 1.5-GSPS ADC
  • Noise spectral density:
    • NSD = -153 dBFS/Hz (no AVG)
    • NSD = -156 dBFS/Hz (2x AVG)
    • NSD = -159 dBFS/Hz (4x AVG)
  • Single core (non-interleaved) ADC architecture
  • Aperture jitter: 50 fs
  • Low close-in residual phase noise:
    • -133 dBc/Hz at 10 kHz offset
  • Spectral performance (f IN = 900 MHz, -4 dBFS):
    • 2x internal averaging
    • SNR: 66.8 dBFS
    • SFDR HD2,3: 74 dBc
    • SFDR worst spur: 90 dBFS
  • Input fullscale: 1.0/1.1 Vpp (1/1.8 dBm)
  • Code error rate (CER): 10 -15
  • Full power input bandwidth (-3 dB): 1.6 GHz
  • JESD204B serial data interface
    • Maximum lane rate: 13 Gbps
    • Supports subclass 1 deterministic latency
  • Digital down-converters
    • Up to four DDC per ADC channel
    • Complex output: 4x, 16x to 128x decimation
    • 48-bit NCO phase coherent frequency hopping
    • Fast frequency hopping: < 1 us
  • Power consumption: 1.8 W/channel (2x AVG)
  • Power supplies: 1.8 V, 1.2 V
  • 14-Bit, dual channel 1.5-GSPS ADC
  • Noise spectral density:
    • NSD = -153 dBFS/Hz (no AVG)
    • NSD = -156 dBFS/Hz (2x AVG)
    • NSD = -159 dBFS/Hz (4x AVG)
  • Single core (non-interleaved) ADC architecture
  • Aperture jitter: 50 fs
  • Low close-in residual phase noise:
    • -133 dBc/Hz at 10 kHz offset
  • Spectral performance (f IN = 900 MHz, -4 dBFS):
    • 2x internal averaging
    • SNR: 66.8 dBFS
    • SFDR HD2,3: 74 dBc
    • SFDR worst spur: 90 dBFS
  • Input fullscale: 1.0/1.1 Vpp (1/1.8 dBm)
  • Code error rate (CER): 10 -15
  • Full power input bandwidth (-3 dB): 1.6 GHz
  • JESD204B serial data interface
    • Maximum lane rate: 13 Gbps
    • Supports subclass 1 deterministic latency
  • Digital down-converters
    • Up to four DDC per ADC channel
    • Complex output: 4x, 16x to 128x decimation
    • 48-bit NCO phase coherent frequency hopping
    • Fast frequency hopping: < 1 us
  • Power consumption: 1.8 W/channel (2x AVG)
  • Power supplies: 1.8 V, 1.2 V

The ADC32RF52 is a single core 14-bit, 1.5 GSPS, dual channel analog to digital converter (ADC) that supports RF sampling with input frequencies up to 2 GHz. The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -153 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -156 dBFS/Hz (2x AVG) and -159 dBFS/Hz (4x AVG).

Each ADC channel can be connected to a quad-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs.

The ADC32RF52 supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13 Gbps.

The power efficient ADC architecture consumes 1.4 W/ch at 1.5 Gsps and provides power scaling with lower sampling rates.

The ADC32RF52 is a single core 14-bit, 1.5 GSPS, dual channel analog to digital converter (ADC) that supports RF sampling with input frequencies up to 2 GHz. The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -153 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -156 dBFS/Hz (2x AVG) and -159 dBFS/Hz (4x AVG).

Each ADC channel can be connected to a quad-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs.

The ADC32RF52 supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13 Gbps.

The power efficient ADC architecture consumes 1.4 W/ch at 1.5 Gsps and provides power scaling with lower sampling rates.
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* Data sheet ADC32RF52 Dual Channel 14-bit 1.5-GSPS RF Sampling Data Converter datasheet PDF | HTML 27 Sep 2023
Application note Improve SFDR Using Calibration in High-Speed ADCs PDF | HTML 19 Jun 2023

Design & development

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Evaluation board

ADC32RF55EVM — ADC32RF55 evaluation module for dual-channel 14-bit 3-GSPS RF-sampling ADC with low NSD

The ADC32RF55 evaluation module (EVM) is a platform for demonstrating the performance of the ADC32RF55 high-speed, JESD204B interface analog-to-digital converter (ADC). Onboard voltage regulation, clocking solution (LMK04832), transformer-coupled analog inputs, and USB interface allow for easy (...)

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Evaluation board

TSW14J58EVM — Data capture/pattern generator: data converter EVM with 16 JESD204B/C lanes from 1.6 to 24.5 Gbps

The TSW14J58 evaluation module (EVM) is a next-generation data capture card used to evaluate the performance of the TI JESD204B/C family of high-speed analog-to-digital converters (ADCs), high-speed digital-to-analog converters (DACs), and analog front ends (AFEs).

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