Product details

Sample rate (max) (Msps) 3000 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 2700 Features High Dynamic Range, High Performance, Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.1 Power consumption (typ) (mW) 4900 SNR (dB) 63.8 ENOB (bit) 10 SFDR (dB) 78 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 3000 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 2700 Features High Dynamic Range, High Performance, Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.1 Power consumption (typ) (mW) 4900 SNR (dB) 63.8 ENOB (bit) 10 SFDR (dB) 78 Operating temperature range (°C) -40 to 85 Input buffer No
VQFNP (RTD) 64 81 mm² 9 x 9
  • 14-Bit, quad channel 3-GSPS ADC
  • Max output rate: 1.5-GSPS
  • Noise spectral density:
    • -156 dBFS/Hz without averaging
    • -158 dBFS/Hz with 2x averaging
  • Single core (non-interleaved) ADC architecture
  • Aperture jitter: 50 fs
  • Low close-in residual phase noise:
    • -127 dBc/Hz at 10 kHz offset
  • Spectral performance (f IN = 0.9 GHz, -4 dBFS):
    • 2x internal averaging
    • SNR: 62.3 dBFS
    • SFDR HD2,3: 63 dBc
    • SFDR worst spur: 85 dBFS
  • Spectral performance (f IN = 1.8 GHz, -4 dBFS):
    • 2x internal averaging
    • SNR: 63 dBFS
    • SFDR HD2,3: 68 dBc
    • SFDR worst spur: 86 dBFS
  • Input full scale: 1.1, 1.35 Vpp (2, 3.5 dBm)
  • Code error rate (CER): 10 -15
  • Full power input bandwidth (-3 dB): 2.75 GHz
  • JESD204B serial data interface
    • Maximum lane rate: 13 Gbps
    • Supports subclass 1 deterministic latency
  • Digital down-converters
    • Up to two DDC per ADC channel
    • Complex output: 4x to 128x decimation
    • 48-bit NCO phase coherent frequency hopping
    • Fast frequency hopping: < 1 µs
  • Power consumption: 1.2 W/channel
  • Power supplies: 1.8 V, 1.2 V
  • 14-Bit, quad channel 3-GSPS ADC
  • Max output rate: 1.5-GSPS
  • Noise spectral density:
    • -156 dBFS/Hz without averaging
    • -158 dBFS/Hz with 2x averaging
  • Single core (non-interleaved) ADC architecture
  • Aperture jitter: 50 fs
  • Low close-in residual phase noise:
    • -127 dBc/Hz at 10 kHz offset
  • Spectral performance (f IN = 0.9 GHz, -4 dBFS):
    • 2x internal averaging
    • SNR: 62.3 dBFS
    • SFDR HD2,3: 63 dBc
    • SFDR worst spur: 85 dBFS
  • Spectral performance (f IN = 1.8 GHz, -4 dBFS):
    • 2x internal averaging
    • SNR: 63 dBFS
    • SFDR HD2,3: 68 dBc
    • SFDR worst spur: 86 dBFS
  • Input full scale: 1.1, 1.35 Vpp (2, 3.5 dBm)
  • Code error rate (CER): 10 -15
  • Full power input bandwidth (-3 dB): 2.75 GHz
  • JESD204B serial data interface
    • Maximum lane rate: 13 Gbps
    • Supports subclass 1 deterministic latency
  • Digital down-converters
    • Up to two DDC per ADC channel
    • Complex output: 4x to 128x decimation
    • 48-bit NCO phase coherent frequency hopping
    • Fast frequency hopping: < 1 µs
  • Power consumption: 1.2 W/channel
  • Power supplies: 1.8 V, 1.2 V

The ADC34RF55 is a single core 14-bit, 3-GSPS, quad channel analog to digital converters (ADC) that support RF sampling with input frequencies up to 3 GHz. The design maximizes signal-to-noise ratio (SNR), and delivers a noise spectral density of -156 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -158 dBFS/Hz.

Each ADC channel can be connected to a dual-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs.

The devices supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13Gbps. There are only 2 serdes lanes per ADC channel. Therefore, in bypass mode, the maximum output data rate supported is 1.5GSPS. When using faster ADC sampling rates on chip, decimation is required.

The power efficient ADC architecture consumes 1.2W/ch and provides power scaling with lower sampling rates.

The ADC34RF55 is a single core 14-bit, 3-GSPS, quad channel analog to digital converters (ADC) that support RF sampling with input frequencies up to 3 GHz. The design maximizes signal-to-noise ratio (SNR), and delivers a noise spectral density of -156 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -158 dBFS/Hz.

Each ADC channel can be connected to a dual-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs.

The devices supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13Gbps. There are only 2 serdes lanes per ADC channel. Therefore, in bypass mode, the maximum output data rate supported is 1.5GSPS. When using faster ADC sampling rates on chip, decimation is required.

The power efficient ADC architecture consumes 1.2W/ch and provides power scaling with lower sampling rates.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* Data sheet ADC34RF55 Quad Channel 14-bit 3-GSPS RF Sampling Data Converter datasheet PDF | HTML 01 Nov 2023
Application note Improve SFDR Using Calibration in High-Speed ADCs PDF | HTML 19 Jun 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC32RF55EVM — ADC32RF55 evaluation module for dual-channel 14-bit 3-GSPS RF-sampling ADC with low NSD

The ADC32RF55 evaluation module (EVM) is a platform for demonstrating the performance of the ADC32RF55 high-speed, JESD204B interface analog-to-digital converter (ADC). Onboard voltage regulation, clocking solution (LMK04832), transformer-coupled analog inputs, and USB interface allow for easy (...)

User guide: PDF | HTML
Not available on TI.com
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Package Pins Download
VQFNP (RTD) 64 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos