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ADC3683-SP

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Radiation-hardness-assured (RHA), QMLV, 300-krad, 18-bit, 2-channel 65MSPS low-latency low-power ADC

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Data sheet

ADC3683-SP

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Data sheet Order now

Product details

Sample rate (max) (Msps) 65 Resolution (Bits) 18 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 400 Features High Dynamic Range, High Performance, Low Power Rating Space Peak-to-peak input voltage range (V) 3.2 Power consumption (typ) (mW) 186 Architecture SAR SNR (dB) 83 ENOB (bit) 13.5 SFDR (dB) 85 Operating temperature range (°C) 25 to 25 Input buffer No Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 75
Sample rate (max) (Msps) 65 Resolution (Bits) 18 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 400 Features High Dynamic Range, High Performance, Low Power Rating Space Peak-to-peak input voltage range (V) 3.2 Power consumption (typ) (mW) 186 Architecture SAR SNR (dB) 83 ENOB (bit) 13.5 SFDR (dB) 85 Operating temperature range (°C) 25 to 25 Input buffer No Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 75
CFP (HBP) 64 118.81 mm² 10.9 x 10.9
  • Space screening and radiation performance
    • QML-V screening and reliability
    • Total ionizing dose (TID): 300 krad (Si)
    • Single event latchup (SEL): 75 MeV-cm2/mg
  • Ambient temperature range: ­−55°C to 105°C
  • Dual channel ADC
  • 18-bit 65MSPS
  • Noise Floor: -160dBFS/Hz
  • Low power and optimized power scaling: 50mW/ch (10MSPS) to 94mW/ch (65MSPS)
  • Latency: 1-2 clock cycles
  • 18-bit, no missing codes
  • INL: ±9, DNL: ±0.7 LSB (typical)
  • Reference: external or internal
  • Input bandwidth: 140MHz (–3dB)
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • Serial LVDS digital interface (2-, 1- and 1/2-wire)
  • Spectral performance (fIN = 5MHz):
    • SNR: 83.5dBFS
    • SFDR: 87dBc HD2, HD3
    • SFDR: 99dBFS worst spur
  • Space screening and radiation performance
    • QML-V screening and reliability
    • Total ionizing dose (TID): 300 krad (Si)
    • Single event latchup (SEL): 75 MeV-cm2/mg
  • Ambient temperature range: ­−55°C to 105°C
  • Dual channel ADC
  • 18-bit 65MSPS
  • Noise Floor: -160dBFS/Hz
  • Low power and optimized power scaling: 50mW/ch (10MSPS) to 94mW/ch (65MSPS)
  • Latency: 1-2 clock cycles
  • 18-bit, no missing codes
  • INL: ±9, DNL: ±0.7 LSB (typical)
  • Reference: external or internal
  • Input bandwidth: 140MHz (–3dB)
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • Serial LVDS digital interface (2-, 1- and 1/2-wire)
  • Spectral performance (fIN = 5MHz):
    • SNR: 83.5dBFS
    • SFDR: 87dBc HD2, HD3
    • SFDR: 99dBFS worst spur

The ADC3683-SP is a low noise, ultra-low power 18-bit 65MSPS high-speed dual channel ADC. Designed for lowest noise performance, the device delivers a noise spectral density of −160dBFS/Hz combined with excellent linearity and dynamic range. The ADC3683-SP offers DC precision together with IF sampling support making it designed for a wide range of applications. High-speed control loops benefit from the short latency as low as only 1 clock cycle. The ADC consumes only 94mW/ch at 65Msps and the power consumption scales well with lower sampling rates.

The device uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device supports two-lane, one-lane and half-lane options. The device is pin-to-pin compatible with the 14-bit, 125MSPS ADC3664-SP. The device comes in a 64-pin CFP package (10.9mm x 10.9mm), and supports a temperature range from −55°C to +105°C.

The ADC3683-SP is a low noise, ultra-low power 18-bit 65MSPS high-speed dual channel ADC. Designed for lowest noise performance, the device delivers a noise spectral density of −160dBFS/Hz combined with excellent linearity and dynamic range. The ADC3683-SP offers DC precision together with IF sampling support making it designed for a wide range of applications. High-speed control loops benefit from the short latency as low as only 1 clock cycle. The ADC consumes only 94mW/ch at 65Msps and the power consumption scales well with lower sampling rates.

The device uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device supports two-lane, one-lane and half-lane options. The device is pin-to-pin compatible with the 14-bit, 125MSPS ADC3664-SP. The device comes in a 64-pin CFP package (10.9mm x 10.9mm), and supports a temperature range from −55°C to +105°C.
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* Data sheet ADC3683-SP Space Grade 18-Bit 1 to 65MSPS, Low Noise, Ultra-low Power Dual Channel ADC datasheet PDF | HTML 08 Mar 2024
EVM User's guide ADC36xxEVMCVAL Evaluation Module User's Guide PDF | HTML 04 Dec 2023

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ADC3683EVMCVAL — ADC3683-SP evaluation module

<p>The ADC3683EVMCVAL is used to evaluate the ADC3683-SP analog-to-digital converter (ADC). ADC3683-SP uses a serial low-voltage differential signaling (LVDS) interface to output the digital data. The serialized LVDS interface supports output rates up to 1Gbps. ADC3683-SP can be operated in (...)

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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