SCES502Q November   2003  – March 2024 SN74AUP1G08

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics, CL = 5 pF
    7. 5.7  Switching Characteristics, CL = 10 pF
    8. 5.8  Switching Characteristics, CL = 15 pF
    9. 5.9  Switching Characteristics, CL = 30 pF
    10. 5.10 Operating Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delays, Setup and Hold Times, and Pulse Duration
    2. 6.2 Enable and Disable Times
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DPW|5
  • DBV|5
  • DSF|6
  • DCK|5
  • YFP|6
  • DRL|5
  • DRY|6
  • YZP|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Data Sheet

SN74AUP1G08 Low-Power Single 2-Input Positive-AND Gate