SCES516M
December 2003 – October 2022
SN74LVC2T45
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics: VCCA = 1.8 V ± 0.15 V
6.7
Switching Characteristics: VCCA = 2.5 V ± 0.2 V
6.8
Switching Characteristics: VCCA = 3.3 V ± 0.3 V
6.9
Switching Characteristics: VCCA = 5 V ± 0.5 V
6.10
Operating Characteristics
6.11
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
8.3.2
Support High-Speed Translation
8.3.3
Ioff Supports Partial-Power-Down Mode Operation
8.3.4
Balanced High-Drive CMOS Push-Pull Outputs
8.3.5
Vcc Isolation
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Unidirectional Logic Level-Shifting Application
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curve
9.2.2
Bidirectional Logic Level-Shifting Application
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.2.1
Enable Times
9.2.2.3
Application Curve
10
Power Supply Recommendations
10.1
Power-Up Considerations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
YZP|8
MXBG020L
DCU|8
MPDS050E
DCT|8
MPDS049D
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sces516m_oa
sces516m_pm
1
Features
Fully configurable dual-rail design allows each port to operate over the full 1.65-V to 5.5-V power-supply range
V
CC
isolation feature – if either V
CC
input is at GND, both ports are in the high-impedance state
DIR input circuit referenced to V
CCA
Low power consumption, 4-μA maximum I
CC
Available in the Texas Instruments
NanoFree™
package
±24-mA output drive at 3.3 V
I
off
supports Partial-Power-Down mode operation
Maximum data rates:
420 Mbps (3.3-V to 5-V translation)
210 Mbps (translate to 3.3 V)
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
Latch-up performance exceeds 100 mA per JESD 78, Class II
ESD protection exceeds JESD 22
4000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)