SN74AUP2G08 Status:ACTIVE

Product Information

Features

• Available in the Texas Instruments NanoFree™ Package
• Low Static-Power Consumption
  (I_CC = 0.9 µA Max)
• Low Dynamic-Power Consumption
  (C_pd = 4.3 pF Typ at 3.3 V)
• Low Input Capacitance (C_i = 1.5 pF Typ)
• Low Noise — Overshoot and Undershoot
  <10% of V_CC
• I_off Supports Partial-Power-Down Mode Operation
• Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input
  (V_hys = 250 mV Typ at 3.3 V)
• Wide Operating V_CC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• t_pd = 4.3 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Performance Tested Per JESD 22
  • 2000-V Human-Body Model
    (A114-B, Class II)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

NanoFree Is a trademark of Texas Instruments

DESCRIPTION/ORDERING INFORMATION

The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

This dual 2-input positive-AND gate performs the Boolean function Y = A • B or Y = (A\ + B\) in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.