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SN74GTLPH1655 Status: ACTIVE

16-Bit LVTTL-To-GTLP Adjustable-Edge-Rate Universal Bus Transceiver


      
         
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 SN74GTLPH1655
Voltage Nodes(V)3.3  
A SideLVTTL  
B SideGTL  
No. of Bits16  
Static Current40  
RatingCatalog  
Technology FamilyGTLP  
 Samples
 Inventory

Customers Who Evaluated This Product Also Evaluated

  • SN74ACT245: Octal Bus Transceivers With 3-State Outputs
  • SN74LVC14A: Hex Schmitt-Trigger Inverter
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    • Product Information

    Features

    • Member of Texas Instruments' Widebus™ Family
    • UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
    • TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes
    • OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
    • Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels
    • Partitioned as Two 8-Bit Transceivers With Individual Latch Timing and Output Control, but With a Common Clock
    • LVTTL Interfaces Are 5-V Tolerant
    • High-Drive GTLP Outputs (100 mA)
    • LVTTL Outputs (�24 mA/24 mA)
    • Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads
    • Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion
    • Bus Hold on A-Port Data Inputs
    • Distributed V CC and GND Pins Minimize High-Speed Switching Noise
    • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
    • ESD Protection Exceeds JESD 22
      • 2000-V Human-Body Model (A114-A)
      • 200-V Machine Model (A115-A)
      • 1000-V Charged-Device Model (C101)

    OEC, TI, TI-OPC, UBT, and Widebus are trademarks of Texas Instruments.

    Description

    The SN74GTLPH1655 is a high-drive, 16-bit UBT™ transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It is partitioned as two 8-bit transceivers and allows for transparent, latched, and clocked modes of data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPc™ circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 11 .

    GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH1655 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels.

    Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage.

    This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.

    This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.

    High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between GND and VCC adjusts the B-port output rise and fall times.This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load.

    Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

    When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE\) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

    		    

    Pricing / Packaging / CAD Design Tools / Samples

    PricePackagingCAD Design ToolsSamples
    DeviceStatusTemp (oC)Price | QuantityPackage | PinsTop Side MarkingPackage QTY | Package CarrierFootprintsSamples
    74GTLPH1655DGGRE4ACTIVE-40 to 856.38 | 1kuTSSOP (DGG) | 64 View 2000 | LARGE T&R Download CAD Format for this Footprint
    74GTLPH1655DGGRG4ACTIVE-40 to 856.38 | 1kuTSSOP (DGG) | 64 View 2000 | LARGE T&R Download CAD Format for this Footprint
    SN74GTLPH1655DGGRACTIVE-40 to 856.38 | 1kuTSSOP (DGG) | 64 View 2000 | LARGE T&R Download CAD Format for this Footprint

    * Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

    Inventory

    Reported Distributor Inventory as of 10:57 AM GMT, 08 Nov 2009
    RegionCompanyIn StockPurchase
    TI Lead Time*: 11 Weeks74GTLPH1655DGGRE4
    WorldwideDigiKey  Available
    TI Lead Time*: 11 Weeks74GTLPH1655DGGRG4
    WorldwideDigiKey  Available
    TI Lead Time*: 11 WeeksSN74GTLPH1655DGGR
    AmericasRochester Electronics >1k
    WorldwideDigiKey >1k
    View all Distributors  

    ** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

    Quality & Lead (Pb)-Free Data

     Product ContentDPPM / MTBF / FIT Rate
    DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
    74GTLPH1655DGGRE4 RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIMViewView
    74GTLPH1655DGGRG4 RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIMViewView
    SN74GTLPH1655DGGR RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIMViewView

    * The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

    If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

    Technical Documents

    Most useful technical documents for SN74GTLPH1655 Help

    Datasheet

    Application Notes

    View Application Notes for Backplane Logic

    User Guides

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    Simulation Models

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    SN74LVC14A Hex Schmitt-Trigger Inverter BUFFERS, DRIVERS AND TRANSCEIVERS-INVERTING BUFFERS AND DRIVERS TI customers also evaluated this product.
    SN74LVC1G08 Single 2-Input Positive-AND Gate LITTLE LOGIC-LL GATE TI customers also evaluated this product.

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