SN74LVT18512 Status: ACTIVE

3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers

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Datasheet

3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers (PDF 762 KB)
01 Oct 1997

	SN74LVT18512
Voltage Nodes(V)	3.3, 2.7
Vcc range(V)	2.7 to 3.6
Input Level	TTL/CMOS
Logic	True
No. of Outputs	18
Output Drive(mA)	-32/64
tpd max(ns)	5.7
Output Level	LVTTL
Static Current	16.5
Rating	Catalog
Technology Family	LVT
	Samples
	Inventory

Product Information

Features

Members of the Texas Instruments SCOPE^TM Family of Testability Products
Members of the Texas Instruments Widebus^TM Family
State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Support Unregulated Battery Operation Down to 2.7 V
UBT^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
B-Port Outputs of 'LVT182512 Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
Compatible With the IEEE Std 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
SCOPE^TM Instruction Set
- IEEE Std 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
- Parallel-Signature Analysis at Inputs
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Device Identification
- Even-Parity Opcodes
Package Options Include 64-Pin Plastic Thin Shrink Small Outline (DGG) and 64-Pin Ceramic Dual Flat (HKC) Packages Using 0.5-mm Center-to-Center Spacings

SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.

Description

The 'LVT18512 and 'LVT182512 scan test devices with 18-bit universal bus transceivers are members of the Texas Instruments SCOPE^TM testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes.

View All Description in Datasheet

Pricing / Packaging / CAD Design Tools / Samples

			Price	Packaging			CAD Design Tools	Samples
Device	Status	Temp (^oC)	Price \| Quantity	Package \| Pins	Top Side Marking	Package QTY \| Package Carrier	Footprints	Samples
74LVT18512DGGRE4	ACTIVE	-40 to 85	6.60 \| 1ku	TSSOP (DGG) \| 64	View	2000 \| LARGE T&R	Contact TI Distributor or Sales Office
74LVT18512DGGRG4	ACTIVE	-40 to 85	6.60 \| 1ku	TSSOP (DGG) \| 64	View	2000 \| LARGE T&R	Contact TI Distributor or Sales Office
SN74LVT18512DGGR	ACTIVE	-40 to 85	6.60 \| 1ku	TSSOP (DGG) \| 64	View	2000 \| LARGE T&R	Contact TI Distributor or Sales Office

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 10:55 AM GMT, 26 Nov 2009
Region	Company	In Stock	Purchase
TI Lead Time*: 20 Weeks74LVT18512DGGRE4
Worldwide	DigiKey	Available
TI Lead Time*: 20 Weeks74LVT18512DGGRG4
Worldwide	DigiKey	Available
TI Lead Time*: 20 WeeksSN74LVT18512DGGR
Americas	Avnet	>1k
Americas	Rochester Electronics	>1k
Worldwide	DigiKey	>1k
View all Distributors

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

	Product Content				DPPM / MTBF / FIT Rate
Device	Eco Plan*	Lead / Ball Finish	MSL Rating / Peak Reflow	Details	Details
74LVT18512DGGRE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
74LVT18512DGGRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74LVT18512DGGR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Most useful technical documents for SN74LVT18512

Datasheet

3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers (PDF, 762 KB)
01 Oct 1997

Application Notes

Input and Output Characteristics of Digital Integrated Circuits (HTM, 9 KB) 9421 views
01 Oct 1996 Read Abstract
Live Insertion (HTM, 8 KB) 2447 views
01 Oct 1996 Read Abstract
Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices (HTM, 9 KB) 1263 views
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TI IBIS File Creation, Validation, and Distribution Processes (HTM, 9 KB) 3911 views
29 Aug 2002 Read Abstract
Shelf-Life Evaluation of Lead-Free Component Finishes (HTM, 8 KB) 27294 views
24 May 2004 Read Abstract
Understanding and Interpreting Standard-Logic Data Sheets (Rev. B) (HTM, 8 KB) 21746 views
28 May 2003 Read Abstract
Understanding Advanced Bus-Interface Products Design Guide (PDF, 253 KB) 4149 views
01 May 1996
16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) (HTM, 8 KB) 1130 views
22 May 2002 Read Abstract
LVT Family Characteristics (Rev. A) (HTM, 8 KB) 967 views
01 Mar 1998 Read Abstract
Implications of Slow or Floating CMOS Inputs (Rev. C) (HTM, 8 KB) 7134 views
01 Feb 1998 Read Abstract
Programming CPLDs Via the 'LVT8986 LASP (HTM, 8 KB) 1217 views
01 Nov 2005 Read Abstract
LVT-to-LVTH Conversion (HTM, 8 KB) 1404 views
08 Dec 1998 Read Abstract
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) (HTM, 8 KB) 2440 views
01 Aug 1997 Read Abstract

View Application Notes for Boundary Scan (JTAG) Bus Devices

User Guides

LOGIC Pocket Data Book (Rev. B) (PDF, 6001 KB) 47453 views
16 Jan 2007
LASP Demo Board User's Guide (PDF, 1209 KB) 762 views
01 Nov 2005

Selection Guides

Logic Guide 2009 (Rev. Z) (PDF, 4263 KB) 90936 views
23 Jul 2009
Advanced Bus Interface Logic Selection Guide (PDF, 464 KB) 7583 views
09 Jan 2001

More Literature

Logic Cross-Reference (Rev. A) (PDF, 2938 KB) 15456 views
07 Oct 2003
Military Low Voltage Solutions (PDF, 103 KB) 776 views
04 Apr 2001

Tools & Software

Name	Part #	Company	Tool / Software Type
Boundary-Scan Logic Models	BSDL	Texas Instruments	Simulators
Scan Educator	SCAN_EDUCATOR	Texas Instruments	Simulators

Simulation Models

BSDL Model
- BSDL Model of SN74LVT18512 (ZIP, 3 KB) 202 views
  06 Dec 2000
IBIS Model
- SN74LVT18512 IBIS Model (Multiple File Format) 159 views
  01 Jun 1999 Read Abstract

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SN74LVT18512 Status: ACTIVE

3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers

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Datasheet

Product Information

Features

Description

Pricing / Packaging / CAD Design Tools / Samples

Inventory

Quality & Lead (Pb)-Free Data

Technical Documents

Datasheet

Application Notes

User Guides

Selection Guides

More Literature

Tools & Software

Simulation Models

Support and Community

Customer Tags

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