SN74LVT8996 Status: ACTIVE

3.3-V ABT 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) TAP Transceiver

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Datasheet

3.3-V 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE Std 1149.1 (JTAG) (Rev. A) (PDF 886 KB)
02 Dec 1999

	SN74LVT8996
Voltage Nodes(V)	3.3, 2.7
Vcc range(V)	2.7 to 3.6
Input Level	TTL/CMOS
Output Level	LVTTL
Rating	Catalog
Technology Family	JTAG
	Samples
	Inventory

Other qualified versions of SN74LVT8996

Version	Part Number	Definition
Enhanced Product	SN74LVT8996-EP	Supports Defense, Aerospace and Medical Applications

Product Information

Features

Members of the Texas Instruments (TI ^TM) Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture
Extend Scan Access From Board Level to Higher Levels of System Integration
Promote Reuse of Lower-Level (Chip/Board) Tests in System Environment
While Powered at 3.3 V, Both the Primary and Secondary TAPs Are Fully 5-V Tolerant for Interfacing to 5-V and/or 3.3-V Masters and Targets
Switch-Based Architecture Allows Direct Connect of Primary TAP to Secondary TAP
Primary TAP Is Multidrop for Minimal Use of Backplane Wiring Channels
Shadow Protocols Can Occur in Any of Test-Logic-Reset, Run-Test/Idle, Pause-DR, and Pause-IR TAP States to Provide for Board-to-Board Test and Built-In Self-Test
Simple Addressing (Shadow) Protocol Is Received/Acknowledged on Primary TAP
10-Bit Address Space Provides for up to 1021 User-Specified Board Addresses
Bypass ( BYP\) Pin Forces Primary-to-Secondary Connection Without Use of Shadow Protocols
Connect ( CON\) Pin Provides Indication of Primary-to-Secondary Connection
High-Drive Outputs (-32-mA I_OH, 64-mA I_OL) Support Backplane Interface at Primary and High Fanout at Secondary
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Package Options Include Plastic Small-Outline (DW) and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic DIPs (JT)

SCOPE and TI are trademarks of Texas Instruments Incorporated.

Description

The 'LVT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments SCOPE^TM testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most SCOPE^TM devices, the ASP is not a boundary-scannable device, rather, it applies TI's addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level.

These devices are functionally equivalent to the 'ABT8996 ASPs. Additionally, they are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to interface to 5-V masters and/or targets.

Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP signals to a set of secondary TAP signals - for example, to interface backplane TAP signals to a board-level TAP.

View All Description in Datasheet

Pricing / Packaging / CAD Design Tools / Samples

			Price	Packaging			CAD Design Tools	Samples
Device	Status	Temp (^oC)	Price \| Quantity	Package \| Pins	Top Side Marking	Package QTY \| Package Carrier	Footprints	Samples
CLVT8996DWG4	ACTIVE	-40 to 85	6.44 \| 1ku	SOIC (DW) \| 24	View	25 \| TUBE	Purchase Samples
SN74LVT8996DW	ACTIVE	-40 to 85	6.44 \| 1ku	SOIC (DW) \| 24	View	25 \| TUBE	Purchase Samples
SN74LVT8996DWR	ACTIVE	-40 to 85	6.86 \| 1ku	SOIC (DW) \| 24	View	2000 \| LARGE T&R	Purchase Samples
SN74LVT8996PW	ACTIVE	-40 to 85	6.44 \| 1ku	TSSOP (PW) \| 24	View	60 \| TUBE	Purchase Samples
SN74LVT8996PWR	ACTIVE	-40 to 85	6.44 \| 1ku	TSSOP (PW) \| 24	View	2000 \| LARGE T&R	Purchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 10:54 AM GMT, 24 Nov 2009
Region	Company	In Stock	Purchase
TI Lead Time*: 16 WeeksCLVT8996DWG4
None Reported View Distributors
TI Lead Time*: 16 WeeksSN74LVT8996DW
Americas	Arrow	725
Americas	Rochester Electronics	251
Europe	EBV Elektronik	25
Worldwide	DigiKey	Available
Worldwide	Mouser Electronics	45
TI Lead Time*: 20 WeeksSN74LVT8996DWR
Americas	Rochester Electronics	>1k
Worldwide	DigiKey	50
TI Lead Time*: 20 WeeksSN74LVT8996PW
Americas	Arrow	>1k
Americas	Rochester Electronics	89
Europe	Arrow Northern Europe	1
Europe	Spoerle	60
TI Lead Time*: 20 WeeksSN74LVT8996PWR
Worldwide	Mouser Electronics	>1k
View all Distributors

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

	Product Content				DPPM / MTBF / FIT Rate
Device	Eco Plan*	Lead / Ball Finish	MSL Rating / Peak Reflow	Details	Details
CLVT8996DWG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74LVT8996DW	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74LVT8996DWR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74LVT8996PW	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74LVT8996PWR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Most useful technical documents for SN74LVT8996

Datasheet

3.3-V 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE Std 1149.1 (JTAG) (Rev. A) (PDF, 886 KB)
02 Dec 1999

Application Notes

Testability Primer (Rev. D) (PDF, 360 KB) 9025 views
11 Mar 2005
Testability Primer (Rev. C) (PDF, 592 KB) 9025 views
01 Oct 1996
Shelf-Life Evaluation of Lead-Free Component Finishes (HTM, 8 KB) 27253 views
24 May 2004 Read Abstract
Cascading Multiple Linking Addressable Scan Port Devices (HTM, 8 KB) 665 views
05 Nov 2002 Read Abstract
Understanding and Interpreting Standard-Logic Data Sheets (Rev. B) (HTM, 8 KB) 21693 views
28 May 2003 Read Abstract

View Application Notes for Boundary Scan (JTAG) Support Devices

User Guides

LOGIC Pocket Data Book (Rev. B) (PDF, 6001 KB) 47354 views
16 Jan 2007

More Literature

Logic Cross-Reference (Rev. A) (PDF, 2938 KB) 15425 views
07 Oct 2003

Tools & Software

Name	Part #	Company	Tool / Software Type
Boundary-Scan Logic Models	BSDL	Texas Instruments	Simulators
Scan Educator	SCAN_EDUCATOR	Texas Instruments	Simulators

Simulation Models

IBIS Model
- SN74LVT8996 IBIS Model (Rev. A) (Multiple File Format) 201 views
  02 Apr 2004 Read Abstract

Support and Community

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SN74LVT8996 Status: ACTIVE

3.3-V ABT 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) TAP Transceiver

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Datasheet

Other qualified versions of SN74LVT8996

Product Information

Features

Description

Pricing / Packaging / CAD Design Tools / Samples

Inventory

Quality & Lead (Pb)-Free Data

Technical Documents

Datasheet

Application Notes

User Guides

More Literature

Tools & Software

Simulation Models

Support and Community

Customer Tags

Other Support