TMS470R1A256 Status: ACTIVE

Product Information

Features

• High-Performance Static CMOS Technology
• TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
  • 24-MHz System Clock (48-MHz Pipeline Mode)
  • Independent 16/32-Bit Instruction Set
  • Open Architecture With Third-Party Support
  • Built-In Debug Module
  • Big-Endian Format Utilized
• Integrated Memory
  • 256K-Byte Program Flash
    • One Bank With 14 Contiguous Sectors
    • Internal State Machine for Programming and Erase
  • 12K-Byte Static RAM (SRAM)
• Operating Features
  • Core Supply Voltage (V_CC): 1.81 V-2.05 V
  • I/O Supply Voltage (V_CCIO): 3.0 V-3.6 V
  • Low-Power Modes: STANDBY and HALT
  • Extended Industrial Temperature Ranges
• 470+ System Module
  • 32-Bit Address Space Decoding
  • Bus Supervision for Memory and Peripherals
  • Analog Watchdog (AWD) Timer
  • Real-Time Interrupt (RTI)
  • System Integrity and Failure Detection
• Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock Module With Prescaler
  • Multiply-by-4 or -8Internal ZPLL Option
  • ZPLL Bypass Mode
• Six Communication Interfaces:
  • Two Serial Peripheral Interfaces (SPIs)
    • 255 Programmable Baud Rates
  • Two Serial Communications Interfaces (SCIs)
    • 2²⁴ Selectable Baud Rates
    • Asynchronous/Isosynchronous Modes
  • Standard CAN Controller (SCC)
    • 16-Mailbox Capacity
    • Fully Compliant With CAN Protocol, Version 2.0B
  • Class II Serial Interface (C2SIb)
    • Two Selectable Data Rates
    • Normal Mode 10.4 Kbps and 4X Mode 41.6 Kbps
• High-End Timer (HET)
  • 16 Programmable I/O Channels:
    • 14 High-Resolution Pins
    • 2 Standard-Resolution Pins
  • High-Resolution Share Feature (XOR)
  • High-End Timer RAM
    • 64-Instruction Capacity
• 10-Bit Multi-Buffered ADC (MibADC) 16-Channel
  • 64-Word FIFO Buffer
  • Single- or Continuous-Conversion Modes
  • 1.55 µs Minimum Sample and Conversion Time
  • Calibration Mode and Self-Test Features
• 8 External Interrupts
• Flexible Interrupt Handling
• 11 Dedicated GIO Pins, 1 Input-Only GIO Pin, and 38 Additional Peripheral I/Os (A256)
• External Clock Prescale (ECP) Module
  • Programmable Low-Frequency External Clock (CLK)
• Compatible ROM Device
• On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1 (JTAG) Test-Access Port⁽¹⁾
• 100-Pin Plastic Low-Profile Quad Flatpack (PZ Suffix)

⁽¹⁾ The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture. Boundary scan is not supported on this device.
⁽²⁾ Throughout the remainder of this document, the TMS470R1A256 device name will be referred to as either the full device name, TMS470R1A256, or as A256.

ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All other trademarks are the property of their respective owners.

Description

The TMS470R1A256⁽²⁾ devices aremembers of the Texas Instruments TMS470R1x family of general-purpose 16/32-bit reduced instruction set computer (RISC) microcontrollers. The A256 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from 0. The TMS470R1A256 utilizes the big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low costs. The A256 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.

The A256 device contains the following:

• ARM7TDMI 16/32-Bit RISC CPU
• TMS470R1x system module (SYS) with 470+ enhancements
• 256K-byte flash
• 12K-byte SRAM
• Zero-pin phase-locked loop (ZPLL) clock module
• Analog watchdog (AWD) timer
• Real-time interrupt (RTI) module
• Two serial peripheral interface (SPI) modules
• Two serial communications interface (SCI) modules
• Standard CAN controller (SCC)
• Class II serial interface (C2SIb)
• 10-bit multi-buffered analog-to-digital converter (MibADC), 16-input channels
• High-end timer (HET) controlling 16 I/Os
• External clock prescale (ECP) module
• Up to 49 I/O pins and 1 input-only pin

The functions performed by the 470+ system module (SYS) include:

• Address decoding
• Memory protection
• Memory and peripherals bus supervision
• Reset and abort exception management
• Prioritization for all internal interrupt sources
• Device clock control
• Parallel signature analysis (PSA)

This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).

The A256 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.

The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. In pipeline mode, the flash operates with a system clock frequency of up to 48 MHz. In normal mode, the flash operates with a system clock frequency of up to 24 MHz. For more detailed information on the flash, see the F05 flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).

The A256 device has six communication interfaces: two SPIs, two SCIs, an SCC, and a C2SIb. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring. The C2SIb allows the A256 to transmit and receive messages on a class II network following an SAE J1850SAE Standard J1850 Class B Data Communication Network Interface standard. For more detailed functional information on the SPI, SCI, and SCC peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197, respectively). For more detailed functional information on the C2SIb peripheral, see the TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214).

The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).

The A256 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).

The A256 device has a 10-bit-resolution sample-and-hold MibADC. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate groupings, two of which are triggerable by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).

The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1-8). The function of the ZPLL is to multiply the external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system (SYS) module. The SYS module subsequently provides the system clock (SYSCLK), real-time interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other A256 device modules. For more detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase Locked Loop (ZPLL) Clock Module Reference Guide (literature number SPNU212).

NOTE: ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal reference.

The A256 device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).