TMS470R1A288 Status:ACTIVE

Product Information

Features

• High-Performance Static CMOS Technology
• TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
  • 24-MHz System Clock (48-MHz Pipeline)
  • Independent 16/32-Bit Instruction Set
  • Open Architecture With Third-Party Support
  • Built-In Debug Module
• Integrated Memory
  • 288K-Byte Program Flash
    • Two Banks With 8 Contiguous Sectors
  • 16K-Byte Static RAM (SRAM)
  • Memory Security Module (MSM)
  • JTAG Security Module
• Operating Features
  • Low-Power Modes: STANDBY and HALT
  • Extended Industrial Temperature Range
• 470+ System Module
  • 32-Bit Address Space Decoding
  • Bus Supervision for Memory/Peripherals
  • Digital Watchdog (DWD) Timer
  • Analog Watchdog (AWD) Timer
  • Enhanced Real-Time Interrupt (RTI)
  • Interrupt Expansion Module (IEM)
  • System Integrity and Failure Detection
  • ICE Breaker
• Direct Memory Access (DMA) Controller
  • 32 Control Packets and 16 Channels
• Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock Module With Prescaler
  • Multiply-by-8 Internal ZPLL Option
  • ZPLL Bypass Mode
• High-End Timer Lite (HET)
  • 12 Programmable I/O Channels: 12 High-Resolution Pins
  • High-Resolution Share Feature (XOR)
  • High-End Timer RAM 64-Instruction Capacity
• External Clock Prescale (ECP) Module
  • Programmable Low-Frequency External Clock (CLK)
• Ten Communication Interfaces:
  • Two Serial Peripheral Interfaces (SPIs)
    • 255 Programmable Baud Rates
  • Two Serial Communication Interfaces (SCIs)
    • 2²⁴ Selectable Baud Rates
    • Asynchronous/Isosynchronous Modes
  • Class II Serial Interface B (C2SIb)
    • Normal 10.4 Kbps and 4X Mode 41.6 Kbps
  • Two Standard CAN Controllers (SCC)
    • 16-Mailbox Capacity
    • Fully Compliant With CAN Protocol, Version 2.0B
  • Three Inter-Integrated Circuit (I2C) Modules
    • Multi-Master and Slave Interfaces
    • Up to 400 Kbps (Fast Mode)
    • 7- and 10-Bit Address Capability
• 12-Channel 10-Bit Multi-Buffered ADC (MibADC)
  • 64-Word FIFO Buffer
  • Single- or Continuous-Conversion Modes
  • 1.55 µs Minimum Sample/Conversion Time
  • Calibration Mode and Self-Test Features
• Flexible Interrupt Handling
• Expansion Bus Module (EBM) (PGE only)
  • Supports 8- and 16-Bit Expansion Bus Memory Interface Mappings
  • 42 I/O Expansion Bus Pins
• 50 Dedicated General-Purpose I/O (GIO) Pins and 43 Additional Peripheral I/Os (PGE)
• 14 Dedicated General-Purpose I/O (GIO) Pins and 43 Additional Peripheral I/Os (PZ)
• 16 External Interrupts
• On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1⁽¹⁾ (JTAG) Test-Access Port
• 144-Pin Plastic Low-Profile Quad Flatpack (PGE Suffix)
• 100-Pin Plastic Low-Profile Quad Flatpack (PZ Suffix)

⁽¹⁾ The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not supported on this device.
⁽²⁾ Throughout the remainder of this document, the TMS470R1A288 will be referred to as either the full device name or as A288.

ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All other trademarks are the property of their respective owners.

Description

The TMS470R1A288⁽²⁾ devices are members ofthe Texas Instruments TMS470R1x family of general-purpose 16/32-bit reduced instruction set computer (RISC) microcontrollers. The A288 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The A288 utilizes the big-endian format where the most significant byte of a word is stored at the lowest-numbered byte and the least significant byte at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low costs. The A288 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.

The A288 devices contain the following:

• ARM7TDMI 16/32-Bit RISC CPU
• TMS470R1x system module (SYS) with 470+ enhancements
• 288K-byte flash
• 16K-byte SRAM
• Zero-pin phase-locked loop (ZPLL) clock module
• Digital watchdog (DWD) timer
• Analog watchdog (AWD) timer
• Enhanced real-time interrupt (RTI) module
• Interrupt expansion module (IEM)
• Memory security module (MSM)
• JTAG security module (JSM)
• Two serial peripheral interface (SPI) modules
• Two serial communications interface (SCI) modules
• Two standard CAN controllers (SCC)
• Three inter-integrated circuit (I2C) modules
• Class II serial interface B (C2SIb) module
• 10-bit multi-buffered analog-to-digital converter (MibADC), with 12 input channels
• High-end timer lite (HET) controlling 12 I/Os
• External clock prescale (ECP)
• Expansion bus module (EBM)
• Up to 93 I/O pins (PGE only), up to 57 I/O (PZ only)

The functions performed by the 470+ system module (SYS) include:

• Address decoding
• Memory protection
• Memory and peripherals bus supervision
• Reset and abort exception management
• Prioritization for all internal interrupt sources
• Device clock control
• Parallel signature analysis (PSA)

The enhanced real-time interrupt (RTI) module on the A288 has the option to be driven by the oscillator clock. The digital watchdog (DWD) is a 25-bit resettable decrementing counter that provides a system reset when the watchdog counter expires. This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).

The A288 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.

The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz. The flash operates with a system clock frequency of up to 24 MHz. For more detailed information on the flash, see the Flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).

The memory security module (MSM) and JTAG security module (JSM) prevent unauthorized access and visibility to on-chip memory, thereby preventing reverse engineering or manipulation of proprietary code. For more information, see the TMS470R1x Memory Security Module Reference Guide (literature number SPNU246) and the TMS470R1x JTAG Security Module Reference Guide (literature number SPNU245).

The A288 device has ten communication interfaces: two SPIs, two SCIs, two SCCs, a C2SI, and three I2Cs. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring. The C2SIb allows the A288 to transmit and receive messages on a class II network following an SAE J1850SAE Standard J1850 Class B Data Communication Network Interface standard. The I2C module is a multi-master communication module providing an interface between the A288 microcontroller and an I2C-compatible device via the I2C serial bus. The I2C supports both 100 Kbps and 400 Kbps speeds. For more detailed functional information on the SPI, SCI, and CAN peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197). For more detailed functional information on the I2C, see the TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number SPNU223). For more detailed functional information on the C2SI, see the TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214).

The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. The HET used in this device is the high-end timer lite. It has fewer I/Os than the usual 32 in a standard HET. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).

The A288HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).

The A288 device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate groupings, two of which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).

The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1-8). The function of the ZPLL is to multiply the external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system (SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other A288 device modules. For more detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide (literature number SPNU212).

NOTE: ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal reference.

The expansion bus module (EBM) is a standalone module that supports the multiplexing of the GIO functions and the expansion bus interface. For more information on the EBM, see the TMS470R1x Expansion Bus Module (EBM) Reference Guide (literature number SPNU222).

The A288 device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).