CDCLVP2106
- Dual 1:6 Differential Buffer
- Two Clock Inputs
- Universal Inputs Can Accept LVPECL, LVDS,
LVCMOS/LVTTL - 12 LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption: 92 mA
- Very Low Additive Jitter: <100 fs,
RMS in 10-kHz to 20-MHz Offset Range - 2.375-V to 3.6-V Device Power Supply
- Maximum Propagation Delay: 550 ps
- Maximum Within Bank Output Skew: 20 ps
- LVPECL Reference Voltage, VAC_REF,
Available for Capacitive-Coupled Inputs - Industrial Temperature Range: –40°C
to +85°C - Supports 105°C PCB Temperature (Measured
with a Thermal Pad) - Available in 6-mm × 6-mm, 40-Pin VQFN
(RHA) Package - ESD Protection Exceeds 2000 V (HBM)
The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP2106 clock buffer distributes two clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2106 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP2106 is characterized for operation from 40°C to +85°C and is available in a 6-mm × 6-mm, VQFN-40 package.
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Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | CDCLVP2106 12-LVPECL Output, High-Performance Clock Buffer datasheet (Rev. B) | PDF | HTML | 25 Oct 2013 |
EVM User's guide | Low Additive Phase Noise Clock Buffer Evaluation Board | 25 Aug 2009 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
CDCLVP2106EVM — CDCLVP2106 Evaluation Module
CLOCK-TREE-ARCHITECT — Clock tree architect programming software
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
Package | Pins | Download |
---|---|---|
VQFN (RHA) | 40 | View options |
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