Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
Up translation:
1.2V to 1.8V
1.5V to 2.5V
1.8V to 3.3V
3.3V to 5.0V
Down translation:
The SN74LV4T125-EP contains four independent buffers with 3-state outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be put into a high impedance (Hi-Z) state by applying a HIGH on the OE pin. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | SN74LV4T125-EP Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter datasheet | PDF | HTML | 31 Jan 2024 |
| * | Radiation & reliability report | SN74LV4T125-EP Enhanced Product Qualification and Reliability Report | PDF | HTML | 08 Mar 2024 |
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The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
| Package | Pins | Download |
|---|---|---|
| TSSOP (PW) | 14 | View options |
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